0676acb6fd
Should cover most of the tests for GVN, GVNHoist, GVNSink, GlobalOpt, GlobalSplit, InstCombine, Reassociate, SROA and TailCallElim that had not been updated earlier.
152 lines
5.4 KiB
LLVM
152 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=gvn -S | FileCheck %s
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; load may be speculated, address is not null using context search.
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; There is a critical edge.
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define i32 @loadpre_critical_edge(i32* align 8 dereferenceable_or_null(48) %arg, i32 %N) nofree nosync {
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; CHECK-LABEL: @loadpre_critical_edge(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[ARG:%.*]], null
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; CHECK-NEXT: br i1 [[CMP]], label [[NULL_EXIT:%.*]], label [[ENTRY_HEADER_CRIT_EDGE:%.*]]
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; CHECK: entry.header_crit_edge:
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; CHECK-NEXT: [[V_PRE:%.*]] = load i32, i32* [[ARG]], align 4
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[V:%.*]] = phi i32 [ [[V_PRE]], [[ENTRY_HEADER_CRIT_EDGE]] ], [ [[SUM:%.*]], [[HEADER]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY_HEADER_CRIT_EDGE]] ], [ [[IV_NEXT:%.*]], [[HEADER]] ]
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; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) #[[ATTR0:[0-9]+]]
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; CHECK-NEXT: [[SUM]] = add i32 [[NEW_V]], [[V]]
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; CHECK-NEXT: store i32 [[SUM]], i32* [[ARG]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 [[SUM]]
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; CHECK: null_exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%cmp = icmp eq i32* %arg, null
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br i1 %cmp, label %null_exit, label %header
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header:
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%iv = phi i32 [0, %entry], [%iv.next, %header]
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; Call prevents to move load over due to it does not guarantee to return.
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%new_v = call i32 @ro_foo(i32 %iv) readnone
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%v = load i32, i32* %arg
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%sum = add i32 %new_v, %v
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store i32 %sum, i32* %arg
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%iv.next = add i32 %iv, 1
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%cond = icmp eq i32 %iv.next, %N
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br i1 %cond, label %exit, label %header
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exit:
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ret i32 %sum
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null_exit:
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ret i32 0
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}
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; load may be speculated, address is not null using context search.
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define i32 @loadpre_basic(i32* align 8 dereferenceable_or_null(48) %arg, i32 %N) nofree nosync {
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; CHECK-LABEL: @loadpre_basic(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[ARG:%.*]], null
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; CHECK-NEXT: br i1 [[CMP]], label [[NULL_EXIT:%.*]], label [[PREHEADER:%.*]]
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; CHECK: preheader:
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; CHECK-NEXT: [[V_PRE:%.*]] = load i32, i32* [[ARG]], align 4
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[V:%.*]] = phi i32 [ [[V_PRE]], [[PREHEADER]] ], [ [[SUM:%.*]], [[HEADER]] ]
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[PREHEADER]] ], [ [[IV_NEXT:%.*]], [[HEADER]] ]
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; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) #[[ATTR0]]
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; CHECK-NEXT: [[SUM]] = add i32 [[NEW_V]], [[V]]
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; CHECK-NEXT: store i32 [[SUM]], i32* [[ARG]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 [[SUM]]
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; CHECK: null_exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%cmp = icmp eq i32* %arg, null
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br i1 %cmp, label %null_exit, label %preheader
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preheader:
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br label %header
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header:
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%iv = phi i32 [0, %preheader], [%iv.next, %header]
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; Call prevents to move load over due to it does not guarantee to return.
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%new_v = call i32 @ro_foo(i32 %iv) readnone
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%v = load i32, i32* %arg
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%sum = add i32 %new_v, %v
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store i32 %sum, i32* %arg
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%iv.next = add i32 %iv, 1
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%cond = icmp eq i32 %iv.next, %N
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br i1 %cond, label %exit, label %header
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exit:
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ret i32 %sum
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null_exit:
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ret i32 0
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}
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; load cannot be speculated, check "address is not null" does not dominate the loop.
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define i32 @loadpre_maybe_null(i32* align 8 dereferenceable_or_null(48) %arg, i32 %N, i1 %c) nofree nosync {
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; CHECK-LABEL: @loadpre_maybe_null(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 [[C:%.*]], label [[NULL_CHECK:%.*]], label [[PREHEADER:%.*]]
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; CHECK: null_check:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32* [[ARG:%.*]], null
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; CHECK-NEXT: br i1 [[CMP]], label [[NULL_EXIT:%.*]], label [[PREHEADER]]
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; CHECK: preheader:
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; CHECK-NEXT: br label [[HEADER:%.*]]
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; CHECK: header:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[PREHEADER]] ], [ [[IV_NEXT:%.*]], [[HEADER]] ]
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; CHECK-NEXT: [[NEW_V:%.*]] = call i32 @ro_foo(i32 [[IV]]) #[[ATTR0]]
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; CHECK-NEXT: [[V:%.*]] = load i32, i32* [[ARG]], align 4
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; CHECK-NEXT: [[SUM:%.*]] = add i32 [[NEW_V]], [[V]]
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; CHECK-NEXT: store i32 [[SUM]], i32* [[ARG]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[IV_NEXT]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[COND]], label [[EXIT:%.*]], label [[HEADER]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 [[SUM]]
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; CHECK: null_exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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br i1 %c, label %null_check, label %preheader
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null_check:
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%cmp = icmp eq i32* %arg, null
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br i1 %cmp, label %null_exit, label %preheader
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preheader:
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br label %header
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header:
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%iv = phi i32 [0, %preheader], [%iv.next, %header]
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; Call prevents to move load over due to it does not guarantee to return.
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%new_v = call i32 @ro_foo(i32 %iv) readnone
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%v = load i32, i32* %arg
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%sum = add i32 %new_v, %v
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store i32 %sum, i32* %arg
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%iv.next = add i32 %iv, 1
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%cond = icmp eq i32 %iv.next, %N
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br i1 %cond, label %exit, label %header
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exit:
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ret i32 %sum
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null_exit:
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ret i32 0
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}
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; Does not guarantee that returns.
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declare i32 @ro_foo(i32) readnone
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