b941857b40
This is another attempt to land this patch. The patch proposed to use a new cost model for loop interchange, which is obtained from loop cache analysis. Given a loopnest, what loop cache analysis returns is a vector of loops [loop0, loop1, loop2, ...] where loop0 should be replaced as the outermost loop, loop1 should be placed one more level inside, and loop2 one more level inside, etc. What loop cache analysis does is not only more comprehensive than the current cost model, it is also a "one-shot" query which means that we only need to query it once during the entire loop interchange pass, which is better than the current cost model where we query it every time we check whether it is profitable to interchange two loops. Thus complexity is reduced, especially after D120386 where we do more interchanges to get the globally optimal loop access pattern. Updates made to test cases are mostly minor changes and some corrections. One change that applies to all tests is that we added an option `-cache-line-size=64` to the RUN lines. This is ensure that loop cache analysis receives a valid number of cache line size for correct analysis. Test coverage for loop interchange is not reduced. Currently we did not completely remove the legacy cost model, but keep it as fall-back in case the new cost model did not run successfully. This is because currently we have some limitations in delinearization, which sometimes makes loop cache analysis bail out. The longer term goal is to enhance delinearization and eventually remove the legacy cost model compeletely. Reviewed By: bmahjour, #loopoptwg Differential Revision: https://reviews.llvm.org/D124926
201 lines
7.9 KiB
LLVM
201 lines
7.9 KiB
LLVM
; RUN: opt < %s -loop-interchange -cache-line-size=64 -loop-interchange-threshold=-100 -verify-loop-lcssa -S | FileCheck %s
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; Test case for PR41725. The induction variables in the latches escape the
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; loops and we must move some PHIs around.
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@a = common dso_local global i64 0, align 4
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@b = common dso_local global i64 0, align 4
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@c = common dso_local global [10 x [10 x i32 ]] zeroinitializer, align 16
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define void @test_lcssa_indvars1() {
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; CHECK-LABEL: @test_lcssa_indvars1()
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; CHECK-LABEL: inner.body:
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; CHECK-NEXT: %iv.inner = phi i64 [ %[[IVNEXT:[0-9]+]], %inner.body.split ], [ 5, %inner.body.preheader ]
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; CHECK-LABEL: inner.body.split:
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; CHECK-NEXT: %0 = phi i64 [ %iv.outer.next, %outer.latch ]
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; CHECK-NEXT: %[[IVNEXT]] = add nsw i64 %iv.inner, -1
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; CHECK-NEXT: %[[COND:[0-9]+]] = icmp eq i64 %iv.inner, 0
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; CHECK-NEXT: br i1 %[[COND]], label %exit, label %inner.body
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; CHECK-LABEL: exit:
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; CHECK-NEXT: %v4.lcssa = phi i64 [ %0, %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa = phi i64 [ %[[IVNEXT]], %inner.body.split ]
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; CHECK-NEXT: store i64 %v8.lcssa.lcssa, i64* @b, align 4
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; CHECK-NEXT: store i64 %v4.lcssa, i64* @a, align 4
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entry:
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br label %outer.header
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outer.header: ; preds = %outer.latch, %entry
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%iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]
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br label %inner.body
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inner.body: ; preds = %inner.body, %outer.header
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%iv.inner = phi i64 [ 5, %outer.header ], [ %iv.inner.next, %inner.body ]
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%v7 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @c, i64 0, i64 %iv.inner, i64 %iv.outer
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store i32 0, i32* %v7, align 4
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%iv.inner.next = add nsw i64 %iv.inner, -1
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%v9 = icmp eq i64 %iv.inner, 0
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br i1 %v9, label %outer.latch, label %inner.body
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outer.latch: ; preds = %inner.body
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%v8.lcssa = phi i64 [ %iv.inner.next, %inner.body ]
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%iv.outer.next = add nuw nsw i64 %iv.outer, 1
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%v5 = icmp ult i64 %iv.outer, 2
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br i1 %v5, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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%v4.lcssa = phi i64 [ %iv.outer.next, %outer.latch ]
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%v8.lcssa.lcssa = phi i64 [ %v8.lcssa, %outer.latch ]
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store i64 %v8.lcssa.lcssa, i64* @b, align 4
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store i64 %v4.lcssa, i64* @a, align 4
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ret void
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}
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define void @test_lcssa_indvars2() {
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; CHECK-LABEL: @test_lcssa_indvars2()
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; CHECK-LABEL: inner.body:
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; CHECK-NEXT: %iv.inner = phi i64 [ %[[IVNEXT:[0-9]+]], %inner.body.split ], [ 5, %inner.body.preheader ]
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; CHECK-LABEL: inner.body.split:
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; CHECK-NEXT: %0 = phi i64 [ %iv.outer, %outer.latch ]
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; CHECK-NEXT: %[[IVNEXT]] = add nsw i64 %iv.inner, -1
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; CHECK-NEXT: %[[COND:[0-9]+]] = icmp eq i64 %[[IVNEXT]], 0
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; CHECK-NEXT: br i1 %[[COND]], label %exit, label %inner.body
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; CHECK-LABEL: exit:
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; CHECK-NEXT: %v4.lcssa = phi i64 [ %0, %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa = phi i64 [ %iv.inner, %inner.body.split ]
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; CHECK-NEXT: store i64 %v8.lcssa.lcssa, i64* @b, align 4
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; CHECK-NEXT: store i64 %v4.lcssa, i64* @a, align 4
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entry:
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br label %outer.header
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outer.header: ; preds = %outer.latch, %entry
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%iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]
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br label %inner.body
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inner.body: ; preds = %inner.body, %outer.header
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%iv.inner = phi i64 [ 5, %outer.header ], [ %iv.inner.next, %inner.body ]
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%v7 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @c, i64 0, i64 %iv.inner, i64 %iv.outer
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store i32 0, i32* %v7, align 4
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%iv.inner.next = add nsw i64 %iv.inner, -1
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%v9 = icmp eq i64 %iv.inner.next, 0
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br i1 %v9, label %outer.latch, label %inner.body
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outer.latch: ; preds = %inner.body
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%v8.lcssa = phi i64 [ %iv.inner, %inner.body ]
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%iv.outer.next = add nuw nsw i64 %iv.outer, 1
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%v5 = icmp ult i64 %iv.outer.next, 2
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br i1 %v5, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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%v4.lcssa = phi i64 [ %iv.outer, %outer.latch ]
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%v8.lcssa.lcssa = phi i64 [ %v8.lcssa, %outer.latch ]
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store i64 %v8.lcssa.lcssa, i64* @b, align 4
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store i64 %v4.lcssa, i64* @a, align 4
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ret void
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}
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define void @test_lcssa_indvars3() {
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; CHECK-LABEL: @test_lcssa_indvars3()
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; CHECK-LABEL: inner.body:
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; CHECK-NEXT: %iv.inner = phi i64 [ %[[IVNEXT:[0-9]+]], %inner.body.split ], [ 5, %inner.body.preheader ]
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; CHECK-LABEL: inner.body.split:
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; CHECK-NEXT: %0 = phi i64 [ %iv.outer.next, %outer.latch ]
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; CHECK-NEXT: %[[IVNEXT]] = add nsw i64 %iv.inner, -1
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; CHECK-NEXT: %[[COND:[0-9]+]] = icmp eq i64 %iv.inner, 0
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; CHECK-NEXT: br i1 %[[COND]], label %exit, label %inner.body
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; CHECK-LABEL: exit:
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; CHECK-NEXT: %v4.lcssa = phi i64 [ %0, %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa = phi i64 [ %[[IVNEXT]], %inner.body.split ]
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; CHECK-NEXT: %v8.lcssa.lcssa.2 = phi i64 [ %[[IVNEXT]], %inner.body.split ]
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; CHECK-NEXT: %r1 = add i64 %v8.lcssa.lcssa, %v8.lcssa.lcssa.2
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; CHECK-NEXT: store i64 %r1, i64* @b, align 4
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; CHECK-NEXT: store i64 %v4.lcssa, i64* @a, align 4
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entry:
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br label %outer.header
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outer.header: ; preds = %outer.latch, %entry
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%iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.latch ]
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br label %inner.body
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inner.body: ; preds = %inner.body, %outer.header
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%iv.inner = phi i64 [ 5, %outer.header ], [ %iv.inner.next, %inner.body ]
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%v7 = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* @c, i64 0, i64 %iv.inner, i64 %iv.outer
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store i32 0, i32* %v7, align 4
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%iv.inner.next = add nsw i64 %iv.inner, -1
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%v9 = icmp eq i64 %iv.inner, 0
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br i1 %v9, label %outer.latch, label %inner.body
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outer.latch: ; preds = %inner.body
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%v8.lcssa = phi i64 [ %iv.inner.next, %inner.body ]
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;%const.lcssa = phi i64 [ 111, %inner.body ]
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%iv.outer.next = add nuw nsw i64 %iv.outer, 1
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%v5 = icmp ult i64 %iv.outer, 2
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br i1 %v5, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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%v4.lcssa = phi i64 [ %iv.outer.next, %outer.latch ]
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%v8.lcssa.lcssa = phi i64 [ %v8.lcssa, %outer.latch ]
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%v8.lcssa.lcssa.2 = phi i64 [ %v8.lcssa, %outer.latch ]
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%r1 = add i64 %v8.lcssa.lcssa, %v8.lcssa.lcssa.2
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store i64 %r1, i64* @b, align 4
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store i64 %v4.lcssa, i64* @a, align 4
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ret void
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}
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; Make sure we do not crash for loops without reachable exits.
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define void @no_reachable_exits() {
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; Check we interchanged.
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; CHECK-LABEL: @no_reachable_exits() {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label %inner.ph
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; CHECK-LABEL: outer.ph:
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; CHECK-NEXT: br label %outer.header
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; CHECK-LABEL: inner.ph:
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; CHECK-NEXT: br label %inner.body
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; CHECK-LABEL: inner.body:
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; CHECK-NEXT: %tmp31 = phi i32 [ 0, %inner.ph ], [ %[[IVNEXT:[0-9]]], %inner.body.split ]
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; CHECK-NEXT: br label %outer.ph
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; CHECK-LABEL: inner.body.split:
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; CHECK-NEXT: %[[IVNEXT]] = add nsw i32 %tmp31, 1
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; CHECK-NEXT: br i1 false, label %inner.body, label %exit
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bb:
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br label %outer.ph
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outer.ph: ; preds = %bb
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br label %outer.header
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outer.header: ; preds = %outer.ph, %outer.latch
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%tmp2 = phi i32 [ 0, %outer.ph ], [ %tmp8, %outer.latch ]
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br i1 undef, label %inner.ph, label %outer.latch
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inner.ph: ; preds = %outer.header
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br label %inner.body
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inner.body: ; preds = %inner.ph, %inner.body
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%tmp31 = phi i32 [ 0, %inner.ph ], [ %tmp6, %inner.body]
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%tmp5 = load i32*, i32** undef, align 8
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%tmp6 = add nsw i32 %tmp31, 1
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br i1 undef, label %inner.body, label %outer.latch
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outer.latch: ; preds = %inner.body, %outer.header
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%tmp8 = add nsw i32 %tmp2, 1
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br i1 undef, label %outer.header, label %exit
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exit: ; preds = %outer.latch
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unreachable
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}
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