99c9b37d11
This is the first patch in a series intended for removing flag -enable-new-pm=0 from lit tests. This is part of a bigger effort of completely removing legacy code related to legacy pass manager in favor of currently default new pass manager. In this patch flag has been removed only from tests where no significant change has been required because checks has been duplicated for both PMs. Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D134150
382 lines
12 KiB
LLVM
382 lines
12 KiB
LLVM
; This test verifies that the loop vectorizer will NOT produce a tail
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; loop with the optimize for size or the minimize size attributes.
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; REQUIRES: asserts
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; RUN: opt < %s -passes='require<profile-summary>,loop-vectorize' -S | FileCheck %s
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; RUN: opt < %s -passes='require<profile-summary>,loop-vectorize' -pgso -S | FileCheck %s -check-prefix=PGSO
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; RUN: opt < %s -passes='require<profile-summary>,loop-vectorize' -pgso=false -S | FileCheck %s -check-prefix=NPGSO
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target datalayout = "E-m:e-p:32:32-i64:32-f64:32:64-a:0:32-n32-S128"
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@tab = common global [32 x i8] zeroinitializer, align 1
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define i32 @foo_optsize() #0 {
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; CHECK-LABEL: @foo_optsize(
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; CHECK-NOT: <2 x i8>
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; CHECK-NOT: <4 x i8>
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%arrayidx = getelementptr inbounds [32 x i8], [32 x i8]* @tab, i32 0, i32 %i.08
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%0 = load i8, i8* %arrayidx, align 1
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%cmp1 = icmp eq i8 %0, 0
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%. = select i1 %cmp1, i8 2, i8 1
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store i8 %., i8* %arrayidx, align 1
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%inc = add nsw i32 %i.08, 1
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%exitcond = icmp eq i32 %i.08, 202
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret i32 0
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}
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attributes #0 = { optsize }
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define i32 @foo_minsize() #1 {
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; CHECK-LABEL: @foo_minsize(
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; CHECK-NOT: <2 x i8>
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; CHECK-NOT: <4 x i8>
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; CHECK-LABEL: @foo_pgso(
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%arrayidx = getelementptr inbounds [32 x i8], [32 x i8]* @tab, i32 0, i32 %i.08
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%0 = load i8, i8* %arrayidx, align 1
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%cmp1 = icmp eq i8 %0, 0
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%. = select i1 %cmp1, i8 2, i8 1
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store i8 %., i8* %arrayidx, align 1
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%inc = add nsw i32 %i.08, 1
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%exitcond = icmp eq i32 %i.08, 202
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret i32 0
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}
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attributes #1 = { minsize }
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define i32 @foo_pgso() !prof !14 {
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; PGSO-LABEL: @foo_pgso(
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; PGSO-NOT: <{{[0-9]+}} x i8>
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; NPGSO-LABEL: @foo_pgso(
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; NPGSO: <{{[0-9]+}} x i8>
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%arrayidx = getelementptr inbounds [32 x i8], [32 x i8]* @tab, i32 0, i32 %i.08
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%0 = load i8, i8* %arrayidx, align 1
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%cmp1 = icmp eq i8 %0, 0
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%. = select i1 %cmp1, i8 2, i8 1
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store i8 %., i8* %arrayidx, align 1
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%inc = add nsw i32 %i.08, 1
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%exitcond = icmp eq i32 %i.08, 202
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret i32 0
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}
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; PR43371: don't run into an assert due to emitting SCEV runtime checks
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; with OptForSize.
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;
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@cm_array = external global [2592 x i16], align 1
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define void @pr43371() optsize {
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;
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; CHECK-LABEL: @pr43371
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; CHECK-NOT: vector.scevcheck
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;
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; We do not want to generate SCEV predicates when optimising for size, because
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; that will lead to extra code generation such as the SCEV overflow runtime
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; checks. Not generating SCEV predicates can still result in vectorisation as
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; the non-consecutive loads/stores can be scalarized:
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;
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; CHECK: vector.body:
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; CHECK: store i16 0, i16* %{{.*}}, align 1
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; CHECK: store i16 0, i16* %{{.*}}, align 1
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; CHECK: br i1 {{.*}}, label %vector.body
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;
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entry:
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br label %for.body29
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for.cond.cleanup28:
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unreachable
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for.body29:
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%i24.0170 = phi i16 [ 0, %entry], [ %inc37, %for.body29]
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%add33 = add i16 undef, %i24.0170
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%idxprom34 = zext i16 %add33 to i32
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%arrayidx35 = getelementptr [2592 x i16], [2592 x i16] * @cm_array, i32 0, i32 %idxprom34
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store i16 0, i16 * %arrayidx35, align 1
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%inc37 = add i16 %i24.0170, 1
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%cmp26 = icmp ult i16 %inc37, 756
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br i1 %cmp26, label %for.body29, label %for.cond.cleanup28
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}
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define void @pr43371_pgso() !prof !14 {
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;
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; CHECK-LABEL: @pr43371_pgso
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; CHECK-NOT: vector.scevcheck
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;
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; We do not want to generate SCEV predicates when optimising for size, because
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; that will lead to extra code generation such as the SCEV overflow runtime
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; checks. Not generating SCEV predicates can still result in vectorisation as
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; the non-consecutive loads/stores can be scalarized:
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;
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; CHECK: vector.body:
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; CHECK: store i16 0, i16* %{{.*}}, align 1
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; CHECK: store i16 0, i16* %{{.*}}, align 1
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; CHECK: br i1 {{.*}}, label %vector.body
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;
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entry:
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br label %for.body29
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for.cond.cleanup28:
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unreachable
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for.body29:
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%i24.0170 = phi i16 [ 0, %entry], [ %inc37, %for.body29]
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%add33 = add i16 undef, %i24.0170
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%idxprom34 = zext i16 %add33 to i32
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%arrayidx35 = getelementptr [2592 x i16], [2592 x i16] * @cm_array, i32 0, i32 %idxprom34
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store i16 0, i16 * %arrayidx35, align 1
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%inc37 = add i16 %i24.0170, 1
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%cmp26 = icmp ult i16 %inc37, 756
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br i1 %cmp26, label %for.body29, label %for.cond.cleanup28
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}
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; PR45526: don't vectorize with fold-tail if first-order-recurrence is live-out.
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;
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define i32 @pr45526() optsize {
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;
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; CHECK-LABEL: @pr45526
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label %loop
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; CHECK-EMPTY:
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; CHECK-NEXT: loop:
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; CHECK-NEXT: %piv = phi i32 [ 0, %entry ], [ %pivPlus1, %loop ]
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; CHECK-NEXT: %for = phi i32 [ 5, %entry ], [ %pivPlus1, %loop ]
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; CHECK-NEXT: %pivPlus1 = add nuw nsw i32 %piv, 1
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; CHECK-NEXT: %cond = icmp ult i32 %piv, 510
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; CHECK-NEXT: br i1 %cond, label %loop, label %exit
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; CHECK-EMPTY:
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; CHECK-NEXT: exit:
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; CHECK-NEXT: %for.lcssa = phi i32 [ %for, %loop ]
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; CHECK-NEXT: ret i32 %for.lcssa
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;
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entry:
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br label %loop
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loop:
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%piv = phi i32 [ 0, %entry ], [ %pivPlus1, %loop ]
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%for = phi i32 [ 5, %entry ], [ %pivPlus1, %loop ]
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%pivPlus1 = add nuw nsw i32 %piv, 1
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%cond = icmp ult i32 %piv, 510
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br i1 %cond, label %loop, label %exit
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exit:
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ret i32 %for
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}
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define i32 @pr45526_pgso() !prof !14 {
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;
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; CHECK-LABEL: @pr45526_pgso
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label %loop
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; CHECK-EMPTY:
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; CHECK-NEXT: loop:
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; CHECK-NEXT: %piv = phi i32 [ 0, %entry ], [ %pivPlus1, %loop ]
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; CHECK-NEXT: %for = phi i32 [ 5, %entry ], [ %pivPlus1, %loop ]
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; CHECK-NEXT: %pivPlus1 = add nuw nsw i32 %piv, 1
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; CHECK-NEXT: %cond = icmp ult i32 %piv, 510
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; CHECK-NEXT: br i1 %cond, label %loop, label %exit
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; CHECK-EMPTY:
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; CHECK-NEXT: exit:
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; CHECK-NEXT: %for.lcssa = phi i32 [ %for, %loop ]
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; CHECK-NEXT: ret i32 %for.lcssa
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;
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entry:
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br label %loop
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loop:
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%piv = phi i32 [ 0, %entry ], [ %pivPlus1, %loop ]
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%for = phi i32 [ 5, %entry ], [ %pivPlus1, %loop ]
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%pivPlus1 = add nuw nsw i32 %piv, 1
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%cond = icmp ult i32 %piv, 510
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br i1 %cond, label %loop, label %exit
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exit:
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ret i32 %for
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}
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; PR46228: Vectorize w/o versioning for unit stride under optsize and enabled
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; vectorization.
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; NOTE: Some assertions have been autogenerated by utils/update_test_checks.py
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define void @stride1(i16* noalias %B, i32 %BStride) optsize {
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; CHECK-LABEL: @stride1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[BSTRIDE:%.*]], i32 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 1>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ule <2 x i32> [[VEC_IND]], <i32 1024, i32 1024>
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; CHECK-NEXT: [[TMP0:%.*]] = mul nsw <2 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
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; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x i1> [[TMP1]], i32 0
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; CHECK-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]]
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; CHECK: pred.store.if:
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP0]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i16, i16* [[B:%.*]], i32 [[TMP3]]
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; CHECK-NEXT: store i16 42, i16* [[TMP4]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE]]
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; CHECK: pred.store.continue:
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; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x i1> [[TMP1]], i32 1
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; CHECK-NEXT: br i1 [[TMP5]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]]
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; CHECK: pred.store.if1:
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; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x i32> [[TMP0]], i32 1
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i16, i16* [[B]], i32 [[TMP6]]
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; CHECK-NEXT: store i16 42, i16* [[TMP7]], align 4
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; CHECK-NEXT: br label [[PRED_STORE_CONTINUE2]]
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; CHECK: pred.store.continue2:
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; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 2
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], <i32 2, i32 2>
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; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1026
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; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !21
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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; PGSO-LABEL: @stride1(
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; PGSO-NEXT: entry:
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; PGSO-NEXT: br i1 false, label %scalar.ph, label %vector.ph
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;
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; NPGSO-LABEL: @stride1(
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; NPGSO-NEXT: entry:
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; NPGSO-NEXT: br i1 false, label %scalar.ph, label %vector.ph
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entry:
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br label %for.body
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for.body:
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%iv = phi i32 [ %iv.next, %for.body ], [ 0, %entry ]
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%mulB = mul nsw i32 %iv, %BStride
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%gepOfB = getelementptr inbounds i16, i16* %B, i32 %mulB
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store i16 42, i16* %gepOfB, align 4
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%iv.next = add nuw nsw i32 %iv, 1
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%exitcond = icmp eq i32 %iv.next, 1025
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br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !15
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for.end:
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ret void
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}
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; Vectorize with versioning for unit stride for PGSO and enabled vectorization.
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;
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define void @stride1_pgso(i16* noalias %B, i32 %BStride) !prof !14 {
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; CHECK-LABEL: @stride1_pgso(
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; CHECK: vector.body
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;
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; PGSO-LABEL: @stride1_pgso(
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; PGSO: vector.body
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;
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; NPGSO-LABEL: @stride1_pgso(
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; NPGSO: vector.body
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entry:
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br label %for.body
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for.body:
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%iv = phi i32 [ %iv.next, %for.body ], [ 0, %entry ]
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%mulB = mul nsw i32 %iv, %BStride
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%gepOfB = getelementptr inbounds i16, i16* %B, i32 %mulB
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store i16 42, i16* %gepOfB, align 4
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%iv.next = add nuw nsw i32 %iv, 1
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%exitcond = icmp eq i32 %iv.next, 1025
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br i1 %exitcond, label %for.end, label %for.body, !llvm.loop !15
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for.end:
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ret void
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}
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; PR46652: Check that the need for stride==1 check prevents vectorizing a loop
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; having tiny trip count, when compiling w/o -Os/-Oz.
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; CHECK-LABEL: @pr46652
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; CHECK-NOT: vector.scevcheck
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; CHECK-NOT: vector.body
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; CHECK-LABEL: for.body
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@g = external global [1 x i16], align 1
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define void @pr46652(i16 %stride) {
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%l1.02 = phi i16 [ 1, %entry ], [ %inc9, %for.body ]
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%mul = mul nsw i16 %l1.02, %stride
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%arrayidx6 = getelementptr inbounds [1 x i16], [1 x i16]* @g, i16 0, i16 %mul
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%0 = load i16, i16* %arrayidx6, align 1
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%inc9 = add nuw nsw i16 %l1.02, 1
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%exitcond.not = icmp eq i16 %inc9, 16
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br i1 %exitcond.not, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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; Make sure we do not crash while building the VPlan for the loop with the
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; select below.
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define i32 @PR48142(i32* %ptr.start, i32* %ptr.end) optsize {
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; CHECK-LABEL: PR48142
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; CHECK-NOT: vector.body
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entry:
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br label %for.body
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for.body:
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%i.014 = phi i32 [ 20, %entry ], [ %cond, %for.body ]
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%ptr.iv = phi i32* [ %ptr.start, %entry ], [ %ptr.next, %for.body ]
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%cmp4 = icmp slt i32 %i.014, 99
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%cond = select i1 %cmp4, i32 99, i32 %i.014
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store i32 0, i32* %ptr.iv
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%ptr.next = getelementptr inbounds i32, i32* %ptr.iv, i64 1
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%cmp.not = icmp eq i32* %ptr.next, %ptr.end
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br i1 %cmp.not, label %exit, label %for.body
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exit:
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%res = phi i32 [ %cond, %for.body ]
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ret i32 %res
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}
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"ProfileSummary", !1}
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!1 = !{!2, !3, !4, !5, !6, !7, !8, !9}
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!2 = !{!"ProfileFormat", !"InstrProf"}
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!3 = !{!"TotalCount", i64 10000}
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!4 = !{!"MaxCount", i64 10}
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!5 = !{!"MaxInternalCount", i64 1}
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!6 = !{!"MaxFunctionCount", i64 1000}
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!7 = !{!"NumCounts", i64 3}
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!8 = !{!"NumFunctions", i64 3}
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!9 = !{!"DetailedSummary", !10}
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!10 = !{!11, !12, !13}
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!11 = !{i32 10000, i64 100, i32 1}
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!12 = !{i32 999000, i64 100, i32 1}
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!13 = !{i32 999999, i64 1, i32 2}
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!14 = !{!"function_entry_count", i64 0}
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!15 = distinct !{!15, !16}
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!16 = !{!"llvm.loop.vectorize.enable", i1 true}
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