Emilio Cota 72d76a2403 [mlir][bufferize] lower allocation alignment from 128 to 64 bytes ...

While it is unlikely to matter in practice, there is no reason
for this value to be larger than it should be. 64 bytes is the
size of a cache line in most machines, and we can fit a full
512-bit vector in it.

Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D139434

2022-12-07 11:12:46 -05:00

..

Transforms

[mlir][bufferize] lower allocation alignment from 128 to 64 bytes

2022-12-07 11:12:46 -05:00

canonicalize.mlir

[mlir] materialize strided memref layout as attribute

2022-08-30 17:19:58 +02:00

inlining.mlir

[mlir][NFC] Update textual references of func to func.func in Bufferization/Complex/EmitC/CF/Func/GPU tests

2022-04-20 22:17:28 -07:00

invalid.mlir

[mlir][bufferization] Support general Attribute as memory space

2022-11-21 09:40:50 -05:00

ops.mlir

[mlir][bufferization] Support general Attribute as memory space

2022-11-21 09:40:50 -05:00