7f8b2e1b91
This was passing in all the parameters needed to construct a LegalizerHelper in the custom legalization, when it's simpler to just pass in the existing helper. This is slightly more annoying to use in the common case where you don't need the legalizer helper, but we could add back the common parameters back in addition to the helper. I didn't propagate this to all the internal target changes that this logically implies, but did update a sample one for legalizeMinNumMaxNum. This is in preparation for moving AMDGPU load/store legalization entirely into custom lowering. The current set of legalization actions is really constraining and not really capable of expressing all the actions needed to legalize loads/stores. In particular there's no way to express when the memory access itself needs to change size vs. the result type. There's also a lot of redundancy since the same split/widen actions need to be applied in both vector and scalar cases. All of the sub-cases logically belong as steps in the legalizer helper, but it will be easier to consider everything at once in custom lowering.
180 lines
8.3 KiB
C++
180 lines
8.3 KiB
C++
//===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the Machinelegalizer class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "AMDGPUArgumentUsageInfo.h"
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#include "SIInstrInfo.h"
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namespace llvm {
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class GCNTargetMachine;
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class LLVMContext;
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class GCNSubtarget;
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/// This class provides the information for the target register banks.
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class AMDGPULegalizerInfo : public LegalizerInfo {
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const GCNSubtarget &ST;
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public:
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AMDGPULegalizerInfo(const GCNSubtarget &ST,
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const GCNTargetMachine &TM);
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bool legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI) const override;
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Register getSegmentAperture(unsigned AddrSpace,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool Signed) const;
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bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool Signed) const;
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bool legalizeMinNumMaxNum(LegalizerHelper &Helper, MachineInstr &MI) const;
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bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeShuffleVector(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool buildPCRelGlobalAddress(
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Register DstReg, LLT PtrTy, MachineIRBuilder &B, const GlobalValue *GV,
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unsigned Offset, unsigned GAFlags = SIInstrInfo::MO_NONE) const;
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bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B,
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GISelChangeObserver &Observer) const;
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bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeAtomicCmpXChg(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFlog(MachineInstr &MI, MachineIRBuilder &B,
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double Log2BaseInverted) const;
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bool legalizeFExp(MachineInstr &MI, MachineIRBuilder &B) const;
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bool legalizeFPow(MachineInstr &MI, MachineIRBuilder &B) const;
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bool legalizeFFloor(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeBuildVector(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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Register getLiveInRegister(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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Register PhyReg, LLT Ty,
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bool InsertLiveInCopy = true) const;
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Register insertLiveInCopy(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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Register LiveIn, Register PhyReg) const;
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const ArgDescriptor *
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getArgDescriptor(MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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bool loadInputValue(Register DstReg, MachineIRBuilder &B,
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const ArgDescriptor *Arg) const;
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bool legalizePreloadedArgIntrin(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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bool legalizeUDIV_UREM(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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void legalizeUDIV_UREM32Impl(MachineIRBuilder &B,
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Register DstReg, Register Num, Register Den,
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bool IsRem) const;
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bool legalizeUDIV_UREM32(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeSDIV_SREM32(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeUDIV_UREM64(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeSDIV_SREM(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIV16(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIV32(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIV64(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFastUnsafeFDIV(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFDIVFastIntrin(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, unsigned AddrSpace) const;
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std::tuple<Register, unsigned, unsigned>
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splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
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Register handleD16VData(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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Register Reg) const;
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bool legalizeRawBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsFormat) const;
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bool legalizeRawBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsFormat) const;
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Register fixStoreSourceType(MachineIRBuilder &B, Register VData,
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bool IsFormat) const;
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bool legalizeBufferStore(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsTyped,
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bool IsFormat) const;
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bool legalizeBufferLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool IsTyped,
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bool IsFormat) const;
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bool legalizeBufferAtomic(MachineInstr &MI, MachineIRBuilder &B,
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Intrinsic::ID IID) const;
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bool legalizeImageIntrinsic(
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MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer,
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const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr) const;
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bool legalizeSBufferLoad(
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MachineInstr &MI, MachineIRBuilder &B,
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GISelChangeObserver &Observer) const;
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bool legalizeAtomicIncDec(MachineInstr &MI, MachineIRBuilder &B,
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bool IsInc) const;
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bool legalizeTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeDebugTrapIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIntrinsic(LegalizerHelper &Helper,
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MachineInstr &MI) const override;
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};
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} // End llvm namespace.
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#endif
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