Kamlesh Kumar 7622ea5835 [RISCV64] Emit correct lib call for fp(float/double) to ui/si ...

Since i32 is not legal in riscv64,
it always promoted to i64 before emitting lib call and
for conversions like float/double to int and float/double to unsigned int
wrong lib call was emitted. This commit fix it using custom lowering.

Differential Revision: https://reviews.llvm.org/D80526

2020-06-18 19:34:16 +05:30

..

AsmParser

[RISCV] Update debug scratch register names

2020-05-05 08:46:07 -07:00

Disassembler

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

MCTargetDesc

[MC] Change MCCFIInstruction::createDefCfa to cfiDefCfa which does not negate Offset

2020-05-22 15:47:26 -07:00

TargetInfo

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Utils

[RISCV] Update debug scratch register names

2020-05-05 08:46:07 -07:00

CMakeLists.txt

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LLVMBuild.txt

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RISCV.h

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RISCV.td

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

RISCVAsmPrinter.cpp

[RISCV] ELF attribute section for RISC-V.

2020-03-31 16:16:19 +08:00

RISCVCallingConv.td

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RISCVCallLowering.cpp

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RISCVCallLowering.h

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RISCVExpandPseudoInsts.cpp

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RISCVFrameLowering.cpp

[MC] Change MCCFIInstruction::createDefCfaOffset to cfiDefCfaOffset which does not negate Offset

2020-05-22 17:07:11 -07:00

RISCVFrameLowering.h

CodeGen: Use Register in TargetFrameLowering

2020-04-07 17:07:44 -04:00

RISCVInstrFormats.td

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RISCVInstrFormatsC.td

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RISCVInstrInfo.cpp

[MachineOutliner] Teach outliner to set live-ins

2020-04-22 14:19:26 -07:00

RISCVInstrInfo.h

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RISCVInstrInfo.td

[RISCV] Add instruction definition for dret

2020-04-24 13:27:43 -07:00

RISCVInstrInfoA.td

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RISCVInstrInfoB.td

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

RISCVInstrInfoC.td

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RISCVInstrInfoD.td

[RISCV] Add patterns for checking isnan

2020-05-02 15:01:04 +01:00

RISCVInstrInfoF.td

[RISCV] Add patterns for checking isnan

2020-05-02 15:01:04 +01:00

RISCVInstrInfoM.td

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RISCVInstructionSelector.cpp

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RISCVISelDAGToDAG.cpp

[RISCV] Support Constant Pools in Load/Store Peephole

2020-05-11 19:20:38 +01:00

RISCVISelDAGToDAG.h

[RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp

2020-04-01 11:30:21 +08:00

RISCVISelLowering.cpp

[RISCV64] Emit correct lib call for fp(float/double) to ui/si

2020-06-18 19:34:16 +05:30

RISCVISelLowering.h

[RISCV] Make visibility of overridden methods in RISCVISelLowering match the parent

2020-06-10 09:16:09 +01:00

RISCVLegalizerInfo.cpp

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RISCVLegalizerInfo.h

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RISCVMachineFunctionInfo.h

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RISCVMCInstLower.cpp

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RISCVMergeBaseOffset.cpp

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RISCVRegisterBankInfo.cpp

Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"

2020-03-20 11:02:50 +01:00

RISCVRegisterBankInfo.h

Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"

2020-03-20 11:02:50 +01:00

RISCVRegisterBanks.td

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RISCVRegisterInfo.cpp

CodeGen: More conversions to use Register

2020-04-07 18:54:36 -04:00

RISCVRegisterInfo.h

CodeGen: More conversions to use Register

2020-04-07 18:54:36 -04:00

RISCVRegisterInfo.td

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RISCVSchedRocket32.td

[RISCV] Add new SchedRead SchedWrite

2020-03-10 00:12:27 +08:00

RISCVSchedRocket64.td

[RISCV] Add new SchedRead SchedWrite

2020-03-10 00:12:27 +08:00

RISCVSchedule.td

[RISCV] Add new SchedRead SchedWrite

2020-03-10 00:12:27 +08:00

RISCVSubtarget.cpp

Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"

2020-03-20 11:02:50 +01:00

RISCVSubtarget.h

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

RISCVSystemOperands.td

[RISCV] Update debug scratch register names

2020-05-05 08:46:07 -07:00

RISCVTargetMachine.cpp

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RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.

2020-05-21 15:23:29 -07:00

RISCVTargetObjectFile.h

[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.

2020-05-21 15:23:29 -07:00

RISCVTargetTransformInfo.cpp

[NFC][CostModel] Add TargetCostKind to relevant APIs

2020-05-05 10:35:54 +01:00

RISCVTargetTransformInfo.h

[NFC][CostModel] Add TargetCostKind to relevant APIs

2020-05-05 10:35:54 +01:00