1657f0ebc2
Global TableGen let override blocks are pretty dangerous and override any local special cases. In this case, the broader HasFlatGlobalInsts was overriding the more specific predicate for FeatureAtomicFaddInsts. Make sure HasFlatGlobalInsts is implied by FeatureAtomicFaddInsts, and make sure the right predicate is used. One issue with independently setting the subtarget features on incompatible targets is all of the encoding families do not define all opcodes. This will hit an assert on gfx10 for example, since we set the encoding independently based on the generation and not based on a feature.
84 lines
3.7 KiB
LLVM
84 lines
3.7 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=gfx908 -verify-machineinstrs | FileCheck %s -check-prefix=GCN
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declare void @llvm.amdgcn.buffer.atomic.fadd.f32(float, <4 x i32>, i32, i32, i1)
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declare void @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half>, <4 x i32>, i32, i32, i1)
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declare void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)*, float)
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declare void @llvm.amdgcn.global.atomic.fadd.p1v2f16.v2f16(<2 x half> addrspace(1)*, <2 x half>)
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; GCN-LABEL: {{^}}buffer_atomic_add_f32:
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; GCN: buffer_atomic_add_f32 v0, v1, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_atomic_add_f32(<4 x i32> inreg %rsrc, float %data, i32 %vindex) {
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main_body:
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call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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ret void
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}
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; GCN-LABEL: {{^}}buffer_atomic_add_f32_off4_slc:
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; GCN: buffer_atomic_add_f32 v0, v1, s[0:3], 0 idxen offset:4 slc
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define amdgpu_ps void @buffer_atomic_add_f32_off4_slc(<4 x i32> inreg %rsrc, float %data, i32 %vindex) {
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main_body:
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call void @llvm.amdgcn.buffer.atomic.fadd.f32(float %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
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ret void
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}
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; GCN-LABEL: {{^}}buffer_atomic_pk_add_v2f16:
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; GCN: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 idxen
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define amdgpu_ps void @buffer_atomic_pk_add_v2f16(<4 x i32> inreg %rsrc, <2 x half> %data, i32 %vindex) {
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main_body:
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call void @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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ret void
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}
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; GCN-LABEL: {{^}}buffer_atomic_pk_add_v2f16_off4_slc:
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; GCN: buffer_atomic_pk_add_f16 v0, v1, s[0:3], 0 idxen offset:4 slc
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define amdgpu_ps void @buffer_atomic_pk_add_v2f16_off4_slc(<4 x i32> inreg %rsrc, <2 x half> %data, i32 %vindex) {
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main_body:
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call void @llvm.amdgcn.buffer.atomic.fadd.v2f16(<2 x half> %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_add_f32:
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; GCN: global_atomic_add_f32 v[{{[0-9:]+}}], v{{[0-9]+}}, off
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define amdgpu_kernel void @global_atomic_add_f32(float addrspace(1)* %ptr, float %data) {
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main_body:
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call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* %ptr, float %data)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_add_f32_off4:
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; GCN: global_atomic_add_f32 v[{{[0-9:]+}}], v{{[0-9]+}}, off offset:4
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define amdgpu_kernel void @global_atomic_add_f32_off4(float addrspace(1)* %ptr, float %data) {
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main_body:
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%p = getelementptr float, float addrspace(1)* %ptr, i64 1
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call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* %p, float %data)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_pk_add_v2f16:
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; GCN: global_atomic_pk_add_f16 v[{{[0-9:]+}}], v{{[0-9]+}}, off
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define amdgpu_kernel void @global_atomic_pk_add_v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
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main_body:
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call void @llvm.amdgcn.global.atomic.fadd.p1v2f16.v2f16(<2 x half> addrspace(1)* %ptr, <2 x half> %data)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_pk_add_v2f16_off4:
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; GCN: global_atomic_pk_add_f16 v[{{[0-9:]+}}], v{{[0-9]+}}, off offset:4
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define amdgpu_kernel void @global_atomic_pk_add_v2f16_off4(<2 x half> addrspace(1)* %ptr, <2 x half> %data) {
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main_body:
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%p = getelementptr <2 x half>, <2 x half> addrspace(1)* %ptr, i64 1
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call void @llvm.amdgcn.global.atomic.fadd.p1v2f16.v2f16(<2 x half> addrspace(1)* %p, <2 x half> %data)
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ret void
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}
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; Make sure this artificially selects with an incorrect subtarget, but
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; the feature set.
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; GCN-LABEL: {{^}}global_atomic_fadd_f32_wrong_subtarget:
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; GCN: global_atomic_add_f32 v[{{[0-9:]+}}], v{{[0-9]+}}, off
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define amdgpu_kernel void @global_atomic_fadd_f32_wrong_subtarget(float addrspace(1)* %ptr, float %data) #0 {
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call void @llvm.amdgcn.global.atomic.fadd.p1f32.f32(float addrspace(1)* %ptr, float %data)
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ret void
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}
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attributes #0 = { "target-cpu"="gfx803" "target-features"="+atomic-fadd-insts" }
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