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clang-p2996/llvm/test/CodeGen/ARM/fp16-bitcast.ll
Lucas Prates a255931c40 [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend 
Summary:
Half-precision floating point arguments and returns are currently
promoted to either float or int32 in clang's CodeGen and there's
no existing support for the lowering of `half` arguments and returns
from IR in AArch32's backend.

Such frontend coercions, implemented as coercion through memory
in clang, can cause a series of issues in argument lowering, as causing
arguments to be stored on the wrong bits on big-endian architectures
and incurring in missing overflow detections in the return of certain
functions.

This patch introduces the handling of half-precision arguments and returns in
the backend using the actual "half" type on the IR. Using the "half"
type the backend is able to properly enforce the AAPCS' directions for
those arguments, making sure they are stored on the proper bits of the
registers and performing the necessary floating point convertions.

Reviewers: rjmccall, olista01, asl, efriedma, ostannard, SjoerdMeijer

Reviewed By: ostannard

Subscribers: stuij, hiraditya, dmgreen, llvm-commits, chill, dnsampaio, danielkiss, kristof.beyls, cfe-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75169
2020-06-18 13:15:13 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple thumbv8m.main-arm-unknown-eabi --float-abi=soft -mattr=+vfp4d16sp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-VFPV4-SOFT
; RUN: llc -mtriple thumbv8.1m.main-arm-unknown-eabi --float-abi=soft -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16-SOFT
; RUN: llc -mtriple thumbv8m.main-arm-unknown-eabi --float-abi=hard -mattr=+vfp4d16sp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-VFPV4-HARD
; RUN: llc -mtriple thumbv8.1m.main-arm-unknown-eabi --float-abi=hard -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16-HARD
target triple = "thumbv8.1m.main-arm-unknown-eabi"
define float @add(float %a, float %b) {
; CHECK-VFPV4-SOFT-LABEL: add:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: vmov s0, r1
; CHECK-VFPV4-SOFT-NEXT: vmov s2, r0
; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s2, s0
; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
; CHECK-VFPV4-SOFT-NEXT: bx lr
;
; CHECK-FP16-SOFT-LABEL: add:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
; CHECK-FP16-SOFT-NEXT: vmov s0, r1
; CHECK-FP16-SOFT-NEXT: vmov s2, r0
; CHECK-FP16-SOFT-NEXT: vadd.f32 s0, s2, s0
; CHECK-FP16-SOFT-NEXT: vmov r0, s0
; CHECK-FP16-SOFT-NEXT: bx lr
;
; CHECK-VFPV4-HARD-LABEL: add:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s0, s1
; CHECK-VFPV4-HARD-NEXT: bx lr
;
; CHECK-FP16-HARD-LABEL: add:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
; CHECK-FP16-HARD-NEXT: vadd.f32 s0, s0, s1
; CHECK-FP16-HARD-NEXT: bx lr
entry:
%add = fadd float %a, %b
ret float %add
}
define half @addf16(half %a, half %b) {
; CHECK-VFPV4-SOFT-LABEL: addf16:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: vmov s2, r1
; CHECK-VFPV4-SOFT-NEXT: vmov s0, r0
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s0, s2
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
; CHECK-VFPV4-SOFT-NEXT: bx lr
;
; CHECK-FP16-SOFT-LABEL: addf16:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, r1
; CHECK-FP16-SOFT-NEXT: vmov.f16 s2, r0
; CHECK-FP16-SOFT-NEXT: vadd.f16 s0, s2, s0
; CHECK-FP16-SOFT-NEXT: vmov r0, s0
; CHECK-FP16-SOFT-NEXT: bx lr
;
; CHECK-VFPV4-HARD-LABEL: addf16:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s2, s1
; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s0, s0
; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s0, s2
; CHECK-VFPV4-HARD-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-HARD-NEXT: bx lr
;
; CHECK-FP16-HARD-LABEL: addf16:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
; CHECK-FP16-HARD-NEXT: vadd.f16 s0, s0, s1
; CHECK-FP16-HARD-NEXT: bx lr
entry:
%add = fadd half %a, %b
ret half %add
}
define half @load_i16(i16 *%hp) {
; CHECK-VFPV4-SOFT-LABEL: load_i16:
; CHECK-VFPV4-SOFT: @ %bb.0: @ %entry
; CHECK-VFPV4-SOFT-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-VFPV4-SOFT-NEXT: ldrh r0, [r0]
; CHECK-VFPV4-SOFT-NEXT: vmov s2, r0
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-VFPV4-SOFT-NEXT: vadd.f32 s0, s2, s0
; CHECK-VFPV4-SOFT-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-SOFT-NEXT: vmov r0, s0
; CHECK-VFPV4-SOFT-NEXT: bx lr
;
; CHECK-FP16-SOFT-LABEL: load_i16:
; CHECK-FP16-SOFT: @ %bb.0: @ %entry
; CHECK-FP16-SOFT-NEXT: vldr.16 s2, [r0]
; CHECK-FP16-SOFT-NEXT: vmov.f16 s0, #1.000000e+00
; CHECK-FP16-SOFT-NEXT: vadd.f16 s0, s2, s0
; CHECK-FP16-SOFT-NEXT: vmov r0, s0
; CHECK-FP16-SOFT-NEXT: bx lr
;
; CHECK-VFPV4-HARD-LABEL: load_i16:
; CHECK-VFPV4-HARD: @ %bb.0: @ %entry
; CHECK-VFPV4-HARD-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-VFPV4-HARD-NEXT: ldrh r0, [r0]
; CHECK-VFPV4-HARD-NEXT: vmov s2, r0
; CHECK-VFPV4-HARD-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-VFPV4-HARD-NEXT: vadd.f32 s0, s2, s0
; CHECK-VFPV4-HARD-NEXT: vcvtb.f16.f32 s0, s0
; CHECK-VFPV4-HARD-NEXT: bx lr
;
; CHECK-FP16-HARD-LABEL: load_i16:
; CHECK-FP16-HARD: @ %bb.0: @ %entry
; CHECK-FP16-HARD-NEXT: vldr.16 s2, [r0]
; CHECK-FP16-HARD-NEXT: vmov.f16 s0, #1.000000e+00
; CHECK-FP16-HARD-NEXT: vadd.f16 s0, s2, s0
; CHECK-FP16-HARD-NEXT: bx lr
entry:
%h = load i16, i16 *%hp, align 2
%hc = bitcast i16 %h to half
%add = fadd half %hc, 1.0
ret half %add
}
define i16 @load_f16(half *%hp) {
; CHECK-LABEL: load_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: ldrh r0, [r0]
; CHECK-NEXT: adds r0, #1
; CHECK-NEXT: bx lr
entry:
%h = load half, half *%hp, align 2
%hc = bitcast half %h to i16
%add = add i16 %hc, 1
ret i16 %add
}
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