b74c6d2c9d
In D74183 clang started emitting alignment for sret parameters
unconditionally. This caused a 1.5% compile-time regression on
tramp3d-v4. The reason is that we now generate many instance of IR like
%ptrint = ptrtoint %class.GuardLayers* %guards_m to i64
%maskedptr = and i64 %ptrint, 3
%maskcond = icmp eq i64 %maskedptr, 0
tail call void @llvm.assume(i1 %maskcond)
to preserve the alignment information during inlining. Based on IR
analysis, these assumptions also regress optimization. The attached
phase ordering test case illustrates two issues: One are instruction
count based optimization heuristics, which are affected by the four
additional instructions of the assumption. The other is blocking of
SROA due to ptrtoint casts (PR45763).
We already encountered the same problem in Rust, where we (unlike
Clang) generally prefer to emit alignment information absolutely
everywhere it is available. We were only able to do this after
hardcoding -preserve-alignment-assumptions-during-inlining=false,
because we were seeing significant optimization and compile-time
regressions otherwise.
This patch disables -preserve-alignment-assumptions-during-inlining
by default, because we should not be punishing people for adding
more alignment annotations.
Once the assume bundle work shakes out and we can represent (and use)
alignment assumptions using assume bundles, it should be possible to
re-enable this with reduced overhead.
Differential Revision: https://reviews.llvm.org/D76886
115 lines
5.0 KiB
LLVM
115 lines
5.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -O2 -preserve-alignment-assumptions-during-inlining=0 < %s | FileCheck %s --check-prefixes=CHECK,ASSUMPTIONS-OFF,FALLBACK-0
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; RUN: opt -S -O2 -preserve-alignment-assumptions-during-inlining=1 < %s | FileCheck %s --check-prefixes=CHECK,ASSUMPTIONS-ON,FALLBACK-1
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; RUN: opt -S -O2 < %s | FileCheck %s --check-prefixes=CHECK,ASSUMPTIONS-OFF,FALLBACK-DEFAULT
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target datalayout = "e-p:64:64-p5:32:32-A5"
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; This illustrates an optimization difference caused by instruction counting
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; heuristics, which are affected by the additional instructions of the
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; alignment assumption.
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define internal i1 @callee1(i1 %c, i64* align 8 %ptr) {
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store volatile i64 0, i64* %ptr
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ret i1 %c
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}
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define void @caller1(i1 %c, i64* align 1 %ptr) {
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; ASSUMPTIONS-OFF-LABEL: @caller1(
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; ASSUMPTIONS-OFF-NEXT: br i1 [[C:%.*]], label [[TRUE2:%.*]], label [[FALSE2:%.*]]
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; ASSUMPTIONS-OFF: true2:
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR:%.*]], align 8
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 2, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: ret void
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; ASSUMPTIONS-OFF: false2:
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 0, i64* [[PTR]], align 8
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 -1, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: store volatile i64 3, i64* [[PTR]], align 4
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; ASSUMPTIONS-OFF-NEXT: ret void
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;
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; ASSUMPTIONS-ON-LABEL: @caller1(
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; ASSUMPTIONS-ON-NEXT: br i1 [[C:%.*]], label [[TRUE1:%.*]], label [[FALSE1:%.*]]
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; ASSUMPTIONS-ON: true1:
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; ASSUMPTIONS-ON-NEXT: [[C_PR:%.*]] = phi i1 [ false, [[FALSE1]] ], [ true, [[TMP0:%.*]] ]
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; ASSUMPTIONS-ON-NEXT: [[PTRINT:%.*]] = ptrtoint i64* [[PTR:%.*]] to i64
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; ASSUMPTIONS-ON-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 7
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; ASSUMPTIONS-ON-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0
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; ASSUMPTIONS-ON-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
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; ASSUMPTIONS-ON-NEXT: store volatile i64 0, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: store volatile i64 -1, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: br i1 [[C_PR]], label [[TRUE2:%.*]], label [[FALSE2:%.*]]
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; ASSUMPTIONS-ON: false1:
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; ASSUMPTIONS-ON-NEXT: store volatile i64 1, i64* [[PTR]], align 4
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; ASSUMPTIONS-ON-NEXT: br label [[TRUE1]]
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; ASSUMPTIONS-ON: true2:
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; ASSUMPTIONS-ON-NEXT: store volatile i64 2, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: ret void
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; ASSUMPTIONS-ON: false2:
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; ASSUMPTIONS-ON-NEXT: store volatile i64 3, i64* [[PTR]], align 8
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; ASSUMPTIONS-ON-NEXT: ret void
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;
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br i1 %c, label %true1, label %false1
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true1:
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%c2 = call i1 @callee1(i1 %c, i64* %ptr)
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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store volatile i64 -1, i64* %ptr
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br i1 %c2, label %true2, label %false2
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false1:
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store volatile i64 1, i64* %ptr
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br label %true1
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true2:
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store volatile i64 2, i64* %ptr
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ret void
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false2:
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store volatile i64 3, i64* %ptr
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ret void
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}
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; This test illustrates that alignment assumptions may prevent SROA.
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; See PR45763.
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define internal void @callee2(i64* noalias sret align 8 %arg) {
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store i64 0, i64* %arg, align 8
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ret void
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}
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define amdgpu_kernel void @caller2() {
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; ASSUMPTIONS-OFF-LABEL: @caller2(
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; ASSUMPTIONS-OFF-NEXT: ret void
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;
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; ASSUMPTIONS-ON-LABEL: @caller2(
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; ASSUMPTIONS-ON-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8, addrspace(5)
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; ASSUMPTIONS-ON-NEXT: [[CAST:%.*]] = addrspacecast i64 addrspace(5)* [[ALLOCA]] to i64*
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; ASSUMPTIONS-ON-NEXT: [[PTRINT:%.*]] = ptrtoint i64* [[CAST]] to i64
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; ASSUMPTIONS-ON-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 7
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; ASSUMPTIONS-ON-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0
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; ASSUMPTIONS-ON-NEXT: call void @llvm.assume(i1 [[MASKCOND]])
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; ASSUMPTIONS-ON-NEXT: ret void
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;
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%alloca = alloca i64, align 8, addrspace(5)
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%cast = addrspacecast i64 addrspace(5)* %alloca to i64*
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call void @callee2(i64* sret align 8 %cast)
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ret void
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}
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