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clang-p2996/llvm/lib/Target/RISCV
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Craig Topper 088bb8a328 [RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1) 
It might be possible to rewrite (and (shl/shr X, C2), C1) in a way
that gives us a left shift that can be folded into a SHXADD.
2022-07-05 16:21:47 -07:00
..
AsmParser
[RISCV] Implement support for the Zicbop extension
2022-06-28 12:43:26 +01:00
Disassembler
Rename MCFixedLenDisassembler.h as MCDecoderOps.h
2022-05-15 08:44:58 +08:00
MCTargetDesc
[MC][RISCV] Suppress R_RISCV_{ADD,SUB}32 in .apple_names .apple_types after D127549
2022-07-01 11:15:04 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCV.h
[RISCV] Pass OptLevel to RISCVDAGToDAGISel correctly
2022-05-30 17:22:50 -07:00
RISCV.td
[RISCV] Implement support for the Zicbop extension
2022-06-28 12:43:26 +01:00
RISCVAsmPrinter.cpp
[RISCV] Lower case the first letter of LowerRISCVMachineOperandToMCOperand. NFC
2022-05-01 14:13:55 -07:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
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RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
[RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.
2022-06-15 16:23:39 +08:00
RISCVFrameLowering.cpp
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
RISCVFrameLowering.h
[RISCV] Restore "Enable shrink wrap by default"
2022-07-02 11:13:13 +08:00
RISCVGatherScatterLowering.cpp
[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
2022-06-10 13:00:20 -07:00
RISCVInsertVSETVLI.cpp
Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
2022-06-29 10:27:02 -07:00
RISCVInstrFormats.td
…
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
RISCVInstrInfo.h
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
RISCVInstrInfo.td
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
RISCVInstrInfoA.td
[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
2022-06-03 09:00:17 -07:00
RISCVInstrInfoC.td
…
RISCVInstrInfoD.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoF.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoM.td
[RISCV] Add isCommutable to ADD/ADDW/MUL/AND/OR/XOR/MIN/MAX/CLMUL
2022-04-25 10:53:41 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Merge the isolated decleration into foreach.
2022-07-05 10:17:45 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove true_mask patterns for VRGATHERE16..
2022-06-21 11:59:37 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Move vfma_vl+fneg_vl matching to DAG combine.
2022-06-24 00:00:37 -07:00
RISCVInstrInfoZb.td
[RISCV] Move some SHXADD matching cases into a ComplexPattern. NFC
2022-07-03 21:57:05 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoZicbo.td
[RISCV] Implement support for the Zicbop extension
2022-06-28 12:43:26 +01:00
RISCVInstrInfoZk.td
…
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Add more SHXADD patterns where the input is (and (shl/shr X, C2), C1)
2022-07-05 16:21:47 -07:00
RISCVISelDAGToDAG.h
[RISCV] Add ADDI instr for computing FrameIndex address
2022-07-04 22:13:35 +08:00
RISCVISelLowering.cpp
[RISCV] Fold (sra (add (shl X, 32), C1), 32 - C) -> (shl (sext_inreg (add X, C1), C)
2022-06-30 09:01:24 -07:00
RISCVISelLowering.h
[RISCV] Move vfma_vl+fneg_vl matching to DAG combine.
2022-06-24 00:00:37 -07:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.cpp
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMachineFunctionInfo.h
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMacroFusion.cpp
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Add pre-emit pass to make more instructions compressible
2022-05-25 09:25:02 +01:00
RISCVMCInstLower.cpp
[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
2022-06-12 10:47:21 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Teach RISCVMergeBaseOffset to handle read-modify-write of a global.
2022-06-28 11:46:24 -07:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
RISCVSchedRocket.td
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RISCVSchedSiFive7.td
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RISCVSchedule.td
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RISCVScheduleB.td
…
RISCVScheduleV.td
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RISCVSExtWRemoval.cpp
[RISCV] transform MI to W variant to remove sext.w
2022-04-22 10:59:26 -07:00
RISCVSubtarget.cpp
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVSubtarget.h
[RISCV] Rename getMin/MaxVLen to getArchMin/MaxVlen and make protected [nfc]
2022-06-28 15:54:40 -07:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVTargetMachine.h
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
2022-04-08 11:55:48 +08:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Cost model for scalable reductions
2022-06-27 12:44:38 -07:00
RISCVTargetTransformInfo.h
[RISCV] Cost model for scalable reductions
2022-06-27 12:44:38 -07:00