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1ed8b29302484b054d74e1db57504687c3ae8709
clang-p2996/llvm/test/Transforms/LoopVectorize/RISCV
History
Philip Reames f239cddbac [RISCV] Pin two tests to fixed length vectorization to preserve test intent
2022-06-28 13:53:31 -07:00
..
illegal-type.ll
[RISCV] Implement isElementTypeLegalForScalableVector TTI hook
2022-06-10 13:20:58 -07:00
lit.local.cfg
…
low-trip-count.ll
[LoopVectorize] Permit tail-folding for low trip counts using scalable vectors
2022-05-16 09:14:24 +01:00
masked_gather_scatter.ll
…
reg-usage.ll
[RISCV] Define risc-v's own register class to model FP Register.
2022-06-06 14:43:52 +08:00
riscv-interleaved.ll
[RISCV] Pin two tests to fixed length vectorization to preserve test intent
2022-06-28 13:53:31 -07:00
riscv-unroll.ll
[RISCV] Pin two tests to fixed length vectorization to preserve test intent
2022-06-28 13:53:31 -07:00
riscv-vector-reverse.ll
[RISCV] Add cost model for reverse shuffle
2022-06-09 07:21:40 -07:00
scalable-basics.ll
[LV] Allow scalable vectorization with vscale = 1
2022-06-27 13:38:57 -07:00
scalable-reductions.ll
Revert "[NFCI] Regenerate SROA/LoopVectorize test checks"
2022-04-04 01:15:30 +02:00
scalable-vf-hint.ll
…
unroll-in-loop-vectorizer.ll
[RISCV] Modify a test line so it exercises the intended configuration once we turn on scalable vectorization
2022-06-24 08:48:11 -07:00
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