Sjoerd Meijer 1ee119f897 Do not expand SDIV when compiling for minimum code size ...

Differential Revision: http://reviews.llvm.org/D22139

llvm-svn: 274855

2016-07-08 15:32:01 +00:00

..

AArch64

[AArch64] Change the preferred alignment for char and short to word alignment.

2016-07-07 20:02:18 +00:00

AMDGPU

AMDGPU: Fix return of non-void-returning shaders

2016-07-06 08:35:17 +00:00

ARM

Do not expand SDIV when compiling for minimum code size

2016-07-08 15:32:01 +00:00

BPF

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Generic

Move CodeGen test from Generic to X86 specific directory

2016-06-10 19:14:01 +00:00

Hexagon

[Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)

2016-06-27 15:08:22 +00:00

Inputs

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Lanai

[lanai] Use peephole optimizer to generate more conditional ALU operations.

2016-07-07 23:36:04 +00:00

Mips

[mips][micromips] Implement LD, LLD, LWU, SD, DSRL, DSRL32 and DSRLV instructions

2016-06-27 08:23:28 +00:00

MIR

[lanai] Use peephole optimizer to generate more conditional ALU operations.

2016-07-07 23:36:04 +00:00

MSP430

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NVPTX

NVPTX: Remove the legacy ptx intrinsics

2016-07-07 16:40:17 +00:00

PowerPC

Ensure all uses of permute instructions feed vector stores

2016-07-06 18:03:52 +00:00

SPARC

Codegen: Fix broken assumption in Tail Merge.

2016-06-24 18:16:36 +00:00

SystemZ

[SystemZ] Remove AND mask of bottom 6 bits when result is used for shift/rotate

2016-07-06 18:13:11 +00:00

Thumb

[Thumb] Reapply r272251 with a fix for PR28348 (mk 2)

2016-07-05 12:37:13 +00:00

Thumb2

[Thumb] Reapply r272251 with a fix for PR28348 (mk 2)

2016-07-05 12:37:13 +00:00

WebAssembly

[WebAssembly] Emit type signatures for declared functions

2016-06-03 18:34:36 +00:00

WinEH

revert http://reviews.llvm.org/D21101

2016-06-30 17:52:24 +00:00

X86

[X86][SSE] Accept any shuffle mask that is all zeroes

2016-07-08 10:39:12 +00:00

XCore

IR: Introduce Module::global_objects().

2016-06-22 20:29:42 +00:00