3b49dc548f
The pass to expand ISEL instructions into if-then-else sequences in patch D23630 is currently disabled. This patch partially enable it by always removing the unnecessary ISELs (all registers used by the ISELs are the same one) and folding the ISELs which have the same input registers into unconditional copies. Differential Revision: https://reviews.llvm.org/D40497 llvm-svn: 320414
55 lines
1.3 KiB
YAML
55 lines
1.3 KiB
YAML
# This file tests the scenario: ISEL RX, RY, RY, CR (X != 0 && Y != 0)
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# It is folded into a copy (%RX = OR %RY, %RY)
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# RUN: llc -ppc-gen-isel=true -run-pass ppc-expand-isel -o - %s | FileCheck %s
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--- |
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define signext i32 @testExpandISEL(i32 signext %i, i32 signext %j) {
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entry:
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%cmp = icmp sgt i32 %i, 0
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%add = add nsw i32 %i, 1
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%cond = select i1 %cmp, i32 %add, i32 %j
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ret i32 %cond
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}
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...
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---
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name: testExpandISEL
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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- { reg: '%x3' }
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- { reg: '%x4' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 0
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adjustsStack: false
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hasCalls: false
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maxCallFrameSize: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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body: |
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bb.0.entry:
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liveins: %x3, %x4
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%r5 = ADDI %r3, 1
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%cr0 = CMPWI %r3, 0
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%r3 = ISEL %r4, %r4, %cr0gt
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; Test fold ISEL to a copy
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; CHECK: %r3 = OR %r4, %r4
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%x3 = EXTSW_32_64 %r3
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...
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