Tian Zhou 8fa432be4f [InstCombine] reduce test-for-overflow of shifted value ...

Fixes #57338.

The added code makes the following transformations:

For unsigned predicates / eq / ne:
icmp pred (x << 1), x --> icmp getSignedPredicate(pred) x, 0
icmp pred x, (x << 1) --> icmp getSignedPredicate(pred) 0, x

Some examples:
https://alive2.llvm.org/ce/z/ckn4cj
https://alive2.llvm.org/ce/z/h-4bAQ

Differential Revision: https://reviews.llvm.org/D132888

2022-09-05 09:51:51 -04:00

..

CMakeLists.txt

…

InstCombineAddSub.cpp

[InstCombine] fold not-shift of signbit to icmp+zext

2022-08-29 10:06:31 -04:00

InstCombineAndOrXor.cpp

[InstCombine] reduce another or-xor bitwise logic pattern

2022-09-03 09:32:08 -04:00

InstCombineAtomicRMW.cpp

[LLVM] Add the support for fmax and fmin in atomicrmw instruction

2022-07-06 10:57:53 -04:00

InstCombineCalls.cpp

Revert "[InstCombine] Treat passing undef to noundef params as UB"

2022-09-02 16:09:50 +05:00

InstCombineCasts.cpp

[InstCombine] delete redundant folds; NFC

2022-08-30 14:21:29 -04:00

InstCombineCompares.cpp

[InstCombine] reduce test-for-overflow of shifted value

2022-09-05 09:51:51 -04:00

InstCombineInternal.h

[InstCombine] add helper function for extract of with-overflow-intrinsic; NFC

2022-08-09 12:38:11 -04:00

InstCombineLoadStoreAlloca.cpp

[Transforms] Qualify auto in range-based for loops (NFC)

2022-08-27 21:21:02 -07:00

InstCombineMulDivRem.cpp

[InstCombine] Distributive or+mul with const operand

2022-08-30 20:36:52 +08:00

InstCombineNegator.cpp

[InstCombine] fold signbit splat pattern that uses negate

2022-08-27 08:04:35 -04:00

InstCombinePHI.cpp

[InstCombine] Improve check for catchswitch BBs (NFC)

2022-06-15 01:06:13 -07:00

InstCombineSelect.cpp

[InstCombine] Change order of canonicalization of ADD and AND

2022-08-22 20:03:53 +01:00

InstCombineShifts.cpp

[InstCombine] Add mul with negated power of 2 constant to canEvaluateShifted.

2022-07-20 11:00:22 -07:00

InstCombineSimplifyDemanded.cpp

[InstCombine] Try not to demand low order bits for Add

2022-08-22 20:03:53 +01:00

InstCombineVectorOps.cpp

[InstCombine] fold fake floating point vector extract to shift+trunc.

2022-08-30 10:12:16 +08:00

InstructionCombining.cpp

[InstCombine] complete fold extractvalue (any_mul_with_overflow X, -1)

2022-09-02 10:58:42 +08:00