0483c91eee
Modifies the GCNDPPCombine pass to enable DPP formation for the new DPP instruction in gfx11, namely VOP3 encoded instructions with DPP and VOPC with DPP. Depends on D128656 Reviewed By: #amdgpu, rampitec Differential Revision: https://reviews.llvm.org/D128682
55 lines
2.4 KiB
LLVM
55 lines
2.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN
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; GCN-LABEL: {{^}}dpp_add:
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; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
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; GCN: v_add_{{(nc_)?}}u32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp_add(i32 addrspace(1)* %arg) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
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%load = load i32, i32 addrspace(1)* %gep
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%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
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%add = add i32 %tmp0, %load
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store i32 %add, i32 addrspace(1)* %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp_ceil:
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; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
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; GCN: v_ceil_f32_dpp [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp_ceil(i32 addrspace(1)* %arg) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
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%load = load i32, i32 addrspace(1)* %gep
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%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i32 %tmp0 to float
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%round = tail call float @llvm.ceil.f32(float %tmp1)
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%tmp2 = bitcast float %round to i32
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store i32 %tmp2, i32 addrspace(1)* %gep
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ret void
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}
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; GCN-LABEL: {{^}}dpp_fadd:
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; GCN: global_load_{{dword|b32}} [[V:v[0-9]+]],
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; GCN: v_add_f32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1{{$}}
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define amdgpu_kernel void @dpp_fadd(i32 addrspace(1)* %arg) {
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%id = tail call i32 @llvm.amdgcn.workitem.id.x()
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id
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%load = load i32, i32 addrspace(1)* %gep
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%tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0
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%tmp1 = bitcast i32 %tmp0 to float
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%t = bitcast i32 %load to float
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%add = fadd float %tmp1, %t
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%tmp2 = bitcast float %add to i32
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store i32 %tmp2, i32 addrspace(1)* %gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
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declare float @llvm.ceil.f32(float)
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attributes #0 = { nounwind readnone convergent }
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