50c743fa71
Similarly as for pointers, even for integers a == b is usually false. GCC also uses this heuristic. Reviewed By: ebrevnov Differential Revision: https://reviews.llvm.org/D85781
170 lines
4.2 KiB
LLVM
170 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; Test 32-bit comparisons in which the second operand is zero-extended
|
|
; from a PC-relative i16.
|
|
;
|
|
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
|
|
|
|
@g = global i16 1
|
|
@h = global i16 1, align 1, section "foo"
|
|
|
|
; Check unsigned comparison.
|
|
define i32 @f1(i32 %src1) {
|
|
; CHECK-LABEL: f1:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: clhrl %r2, g
|
|
; CHECK-NEXT: jhe .LBB0_2
|
|
; CHECK-NEXT: # %bb.1: # %exit
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
; CHECK-NEXT: .LBB0_2: # %mulb
|
|
; CHECK-NEXT: msr %r2, %r2
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
entry:
|
|
%val = load i16, i16 *@g
|
|
%src2 = zext i16 %val to i32
|
|
%cond = icmp ult i32 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i32 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
|
|
%res = add i32 %tmp, 1
|
|
ret i32 %res
|
|
}
|
|
|
|
; Check signed comparison.
|
|
define i32 @f2(i32 %src1) {
|
|
; CHECK-LABEL: f2:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: llhrl %r0, g
|
|
; CHECK-NEXT: crjhe %r2, %r0, .LBB1_2
|
|
; CHECK-NEXT: # %bb.1: # %exit
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
; CHECK-NEXT: .LBB1_2: # %mulb
|
|
; CHECK-NEXT: msr %r2, %r2
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
entry:
|
|
%val = load i16, i16 *@g
|
|
%src2 = zext i16 %val to i32
|
|
%cond = icmp slt i32 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i32 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
|
|
%res = add i32 %tmp, 1
|
|
ret i32 %res
|
|
}
|
|
|
|
; Check equality.
|
|
define i32 @f3(i32 %src1) {
|
|
; CHECK-LABEL: f3:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: clhrl %r2, g
|
|
; CHECK-NEXT: je .LBB2_2
|
|
; CHECK-NEXT: # %bb.1: # %mulb
|
|
; CHECK-NEXT: msr %r2, %r2
|
|
; CHECK-NEXT: .LBB2_2: # %exit
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
entry:
|
|
%val = load i16, i16 *@g
|
|
%src2 = zext i16 %val to i32
|
|
%cond = icmp eq i32 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i32 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
|
|
%res = add i32 %tmp, 1
|
|
ret i32 %res
|
|
}
|
|
|
|
; Check inequality.
|
|
define i32 @f4(i32 %src1) {
|
|
; CHECK-LABEL: f4:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: clhrl %r2, g
|
|
; CHECK-NEXT: je .LBB3_2
|
|
; CHECK-NEXT: # %bb.1: # %exit
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
; CHECK-NEXT: .LBB3_2: # %mulb
|
|
; CHECK-NEXT: msr %r2, %r2
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
entry:
|
|
%val = load i16, i16 *@g
|
|
%src2 = zext i16 %val to i32
|
|
%cond = icmp ne i32 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i32 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
|
|
%res = add i32 %tmp, 1
|
|
ret i32 %res
|
|
}
|
|
|
|
; Repeat f1 with an unaligned address.
|
|
define i32 @f5(i32 %src1) {
|
|
; CHECK-LABEL: f5:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: lgrl %r1, h@GOT
|
|
; CHECK-NEXT: llh %r0, 0(%r1)
|
|
; CHECK-NEXT: clrjhe %r2, %r0, .LBB4_2
|
|
; CHECK-NEXT: # %bb.1: # %exit
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
; CHECK-NEXT: .LBB4_2: # %mulb
|
|
; CHECK-NEXT: msr %r2, %r2
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
entry:
|
|
%val = load i16, i16 *@h, align 1
|
|
%src2 = zext i16 %val to i32
|
|
%cond = icmp ult i32 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i32 %src1, %src1
|
|
br label %exit
|
|
exit:
|
|
%tmp = phi i32 [ %src1, %entry ], [ %mul, %mulb ]
|
|
%res = add i32 %tmp, 1
|
|
ret i32 %res
|
|
}
|
|
|
|
; Check the comparison can be reversed if that allows CLHRL to be used.
|
|
define i32 @f6(i32 %src2) {
|
|
; CHECK-LABEL: f6:
|
|
; CHECK: # %bb.0: # %entry
|
|
; CHECK-NEXT: clhrl %r2, g
|
|
; CHECK-NEXT: jle .LBB5_2
|
|
; CHECK-NEXT: # %bb.1: # %exit
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
; CHECK-NEXT: .LBB5_2: # %mulb
|
|
; CHECK-NEXT: msr %r2, %r2
|
|
; CHECK-NEXT: ahi %r2, 1
|
|
; CHECK-NEXT: br %r14
|
|
entry:
|
|
%val = load i16, i16 *@g
|
|
%src1 = zext i16 %val to i32
|
|
%cond = icmp ult i32 %src1, %src2
|
|
br i1 %cond, label %exit, label %mulb
|
|
mulb:
|
|
%mul = mul i32 %src2, %src2
|
|
br label %exit
|
|
exit:
|
|
%tmp = phi i32 [ %src2, %entry ], [ %mul, %mulb ]
|
|
%res = add i32 %tmp, 1
|
|
ret i32 %res
|
|
}
|