17db0de330
Init captures added in processBlock() to avoid capturing structured bindings, which caused the build problems (with clang). RISCV has this disabled for now until problems relating to post RA pseudo expansions are resolved.
241 lines
8.3 KiB
C++
241 lines
8.3 KiB
C++
//==--- MachineLateInstrsCleanup.cpp - Late Instructions Cleanup Pass -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This simple pass removes any identical and redundant immediate or address
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// loads to the same register. The immediate loads removed can originally be
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// the result of rematerialization, while the addresses are redundant frame
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// addressing anchor points created during Frame Indices elimination.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-latecleanup"
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STATISTIC(NumRemoved, "Number of redundant instructions removed.");
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namespace {
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class MachineLateInstrsCleanup : public MachineFunctionPass {
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const TargetRegisterInfo *TRI;
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const TargetInstrInfo *TII;
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// Data structures to map regs to their definitions per MBB.
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using Reg2DefMap = std::map<Register, MachineInstr*>;
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std::vector<Reg2DefMap> RegDefs;
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// Walk through the instructions in MBB and remove any redundant
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// instructions.
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bool processBlock(MachineBasicBlock *MBB);
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public:
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static char ID; // Pass identification, replacement for typeid
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MachineLateInstrsCleanup() : MachineFunctionPass(ID) {
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initializeMachineLateInstrsCleanupPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::NoVRegs);
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}
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};
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} // end anonymous namespace
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char MachineLateInstrsCleanup::ID = 0;
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char &llvm::MachineLateInstrsCleanupID = MachineLateInstrsCleanup::ID;
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INITIALIZE_PASS(MachineLateInstrsCleanup, DEBUG_TYPE,
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"Machine Late Instructions Cleanup Pass", false, false)
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bool MachineLateInstrsCleanup::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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bool Changed = false;
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TRI = MF.getSubtarget().getRegisterInfo();
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TII = MF.getSubtarget().getInstrInfo();
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RegDefs.clear();
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RegDefs.resize(MF.getNumBlockIDs());
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// Visit all MBBs in an order that maximises the reuse from predecessors.
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ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
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for (MachineBasicBlock *MBB : RPOT)
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Changed |= processBlock(MBB);
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return Changed;
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}
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// Clear any previous kill flag on Reg found before I in MBB. Walk backwards
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// in MBB and if needed continue in predecessors until a use/def of Reg is
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// encountered. This seems to be faster in practice than tracking kill flags
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// in a map.
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static void clearKillsForDef(Register Reg, MachineBasicBlock *MBB,
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MachineBasicBlock::iterator I,
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BitVector &VisitedPreds,
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const TargetRegisterInfo *TRI) {
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VisitedPreds.set(MBB->getNumber());
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while (I != MBB->begin()) {
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I--;
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bool Found = false;
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for (auto &MO : I->operands())
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if (MO.isReg() && TRI->regsOverlap(MO.getReg(), Reg)) {
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if (MO.isDef())
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return;
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if (MO.readsReg()) {
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MO.setIsKill(false);
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Found = true; // Keep going for an implicit kill of the super-reg.
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}
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}
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if (Found)
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return;
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}
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// If an earlier def is not in MBB, continue in predecessors.
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if (!MBB->isLiveIn(Reg))
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MBB->addLiveIn(Reg);
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assert(!MBB->pred_empty() && "Predecessor def not found!");
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for (MachineBasicBlock *Pred : MBB->predecessors())
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if (!VisitedPreds.test(Pred->getNumber()))
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clearKillsForDef(Reg, Pred, Pred->end(), VisitedPreds, TRI);
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}
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static void removeRedundantDef(MachineInstr *MI,
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const TargetRegisterInfo *TRI) {
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Register Reg = MI->getOperand(0).getReg();
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BitVector VisitedPreds(MI->getMF()->getNumBlockIDs());
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clearKillsForDef(Reg, MI->getParent(), MI->getIterator(), VisitedPreds, TRI);
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MI->eraseFromParent();
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++NumRemoved;
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}
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// Return true if MI is a potential candidate for reuse/removal and if so
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// also the register it defines in DefedReg. A candidate is a simple
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// instruction that does not touch memory, has only one register definition
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// and the only reg it may use is FrameReg. Typically this is an immediate
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// load or a load-address instruction.
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static bool isCandidate(const MachineInstr *MI, Register &DefedReg,
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Register FrameReg) {
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DefedReg = MCRegister::NoRegister;
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bool SawStore = true;
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if (!MI->isSafeToMove(nullptr, SawStore) || MI->isImplicitDef() ||
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MI->isInlineAsm())
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return false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isReg()) {
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if (MO.isDef()) {
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if (i == 0 && !MO.isImplicit() && !MO.isDead())
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DefedReg = MO.getReg();
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else
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return false;
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} else if (MO.getReg() && MO.getReg() != FrameReg)
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return false;
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} else if (!(MO.isImm() || MO.isCImm() || MO.isFPImm() || MO.isCPI() ||
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MO.isGlobal() || MO.isSymbol()))
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return false;
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}
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return DefedReg.isValid();
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}
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bool MachineLateInstrsCleanup::processBlock(MachineBasicBlock *MBB) {
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bool Changed = false;
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Reg2DefMap &MBBDefs = RegDefs[MBB->getNumber()];
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// Find reusable definitions in the predecessor(s).
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if (!MBB->pred_empty()) {
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MachineBasicBlock *FirstPred = *MBB->pred_begin();
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for (auto [Reg, DefMI] : RegDefs[FirstPred->getNumber()])
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if (llvm::all_of(
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drop_begin(MBB->predecessors()),
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[&, &Reg = Reg, &DefMI = DefMI](const MachineBasicBlock *Pred) {
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auto PredDefI = RegDefs[Pred->getNumber()].find(Reg);
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return PredDefI != RegDefs[Pred->getNumber()].end() &&
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DefMI->isIdenticalTo(*PredDefI->second);
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})) {
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MBBDefs[Reg] = DefMI;
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LLVM_DEBUG(dbgs() << "Reusable instruction from pred(s): in "
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<< printMBBReference(*MBB) << ": " << *DefMI;);
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}
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}
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// Process MBB.
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MachineFunction *MF = MBB->getParent();
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const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
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Register FrameReg = TRI->getFrameRegister(*MF);
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for (MachineInstr &MI : llvm::make_early_inc_range(*MBB)) {
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// If FrameReg is modified, no previous load-address instructions are valid.
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if (MI.modifiesRegister(FrameReg, TRI)) {
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MBBDefs.clear();
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continue;
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}
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Register DefedReg;
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bool IsCandidate = isCandidate(&MI, DefedReg, FrameReg);
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// Check for an earlier identical and reusable instruction.
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if (IsCandidate) {
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auto DefI = MBBDefs.find(DefedReg);
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if (DefI != MBBDefs.end() && MI.isIdenticalTo(*DefI->second)) {
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LLVM_DEBUG(dbgs() << "Removing redundant instruction in "
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<< printMBBReference(*MBB) << ": " << MI;);
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removeRedundantDef(&MI, TRI);
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Changed = true;
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continue;
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}
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}
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// Clear any entries in map that MI clobbers.
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for (auto DefI = MBBDefs.begin(); DefI != MBBDefs.end();) {
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Register Reg = DefI->first;
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if (MI.modifiesRegister(Reg, TRI))
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DefI = MBBDefs.erase(DefI);
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else
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++DefI;
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}
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// Record this MI for potential later reuse.
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if (IsCandidate) {
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LLVM_DEBUG(dbgs() << "Found interesting instruction in "
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<< printMBBReference(*MBB) << ": " << MI;);
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MBBDefs[DefedReg] = &MI;
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}
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}
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return Changed;
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}
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