2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
332 lines
11 KiB
C++
332 lines
11 KiB
C++
//===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "SIMachineFunctionInfo.h"
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#include "AMDGPUArgumentUsageInfo.h"
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#include "AMDGPUSubtarget.h"
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#include "SIRegisterInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Function.h"
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#include <cassert>
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#include <vector>
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#define MAX_LANES 64
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using namespace llvm;
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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PrivateSegmentBuffer(false),
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DispatchPtr(false),
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QueuePtr(false),
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KernargSegmentPtr(false),
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DispatchID(false),
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FlatScratchInit(false),
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WorkGroupIDX(false),
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WorkGroupIDY(false),
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WorkGroupIDZ(false),
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WorkGroupInfo(false),
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PrivateSegmentWaveByteOffset(false),
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WorkItemIDX(false),
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WorkItemIDY(false),
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WorkItemIDZ(false),
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ImplicitBufferPtr(false),
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ImplicitArgPtr(false),
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GITPtrHigh(0xffffffff),
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HighBitsOf32BitAddress(0) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const Function &F = MF.getFunction();
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FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
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WavesPerEU = ST.getWavesPerEU(F);
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Occupancy = getMaxWavesPerEU();
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limitOccupancy(MF);
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CallingConv::ID CC = F.getCallingConv();
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if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
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if (!F.arg_empty())
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KernargSegmentPtr = true;
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WorkGroupIDX = true;
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WorkItemIDX = true;
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} else if (CC == CallingConv::AMDGPU_PS) {
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PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
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}
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if (!isEntryFunction()) {
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// Non-entry functions have no special inputs for now, other registers
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// required for scratch access.
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ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
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ScratchWaveOffsetReg = AMDGPU::SGPR4;
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FrameOffsetReg = AMDGPU::SGPR5;
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StackPtrOffsetReg = AMDGPU::SGPR32;
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ArgInfo.PrivateSegmentBuffer =
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ArgDescriptor::createRegister(ScratchRSrcReg);
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ArgInfo.PrivateSegmentWaveByteOffset =
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ArgDescriptor::createRegister(ScratchWaveOffsetReg);
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if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
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ImplicitArgPtr = true;
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} else {
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if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
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KernargSegmentPtr = true;
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MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
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MaxKernArgAlign);
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}
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}
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if (ST.debuggerEmitPrologue()) {
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// Enable everything.
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WorkGroupIDX = true;
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WorkGroupIDY = true;
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WorkGroupIDZ = true;
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WorkItemIDX = true;
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WorkItemIDY = true;
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WorkItemIDZ = true;
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} else {
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if (F.hasFnAttribute("amdgpu-work-group-id-x"))
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WorkGroupIDX = true;
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if (F.hasFnAttribute("amdgpu-work-group-id-y"))
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WorkGroupIDY = true;
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if (F.hasFnAttribute("amdgpu-work-group-id-z"))
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WorkGroupIDZ = true;
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if (F.hasFnAttribute("amdgpu-work-item-id-x"))
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WorkItemIDX = true;
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if (F.hasFnAttribute("amdgpu-work-item-id-y"))
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WorkItemIDY = true;
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if (F.hasFnAttribute("amdgpu-work-item-id-z"))
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WorkItemIDZ = true;
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}
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const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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bool HasStackObjects = FrameInfo.hasStackObjects();
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if (isEntryFunction()) {
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// X, XY, and XYZ are the only supported combinations, so make sure Y is
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// enabled if Z is.
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if (WorkItemIDZ)
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WorkItemIDY = true;
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PrivateSegmentWaveByteOffset = true;
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// HS and GS always have the scratch wave offset in SGPR5 on GFX9.
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if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
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(CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
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ArgInfo.PrivateSegmentWaveByteOffset =
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ArgDescriptor::createRegister(AMDGPU::SGPR5);
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}
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bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
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if (isAmdHsaOrMesa) {
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PrivateSegmentBuffer = true;
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if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
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DispatchPtr = true;
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if (F.hasFnAttribute("amdgpu-queue-ptr"))
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QueuePtr = true;
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if (F.hasFnAttribute("amdgpu-dispatch-id"))
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DispatchID = true;
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} else if (ST.isMesaGfxShader(F)) {
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ImplicitBufferPtr = true;
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}
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if (F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
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KernargSegmentPtr = true;
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if (ST.hasFlatAddressSpace() && isEntryFunction() && isAmdHsaOrMesa) {
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// TODO: This could be refined a lot. The attribute is a poor way of
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// detecting calls that may require it before argument lowering.
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if (HasStackObjects || F.hasFnAttribute("amdgpu-flat-scratch"))
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FlatScratchInit = true;
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}
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Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
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StringRef S = A.getValueAsString();
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if (!S.empty())
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S.consumeInteger(0, GITPtrHigh);
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A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
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S = A.getValueAsString();
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if (!S.empty())
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S.consumeInteger(0, HighBitsOf32BitAddress);
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}
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void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
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limitOccupancy(getMaxWavesPerEU());
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const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
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limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
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MF.getFunction()));
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}
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unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
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const SIRegisterInfo &TRI) {
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ArgInfo.PrivateSegmentBuffer =
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ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass));
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NumUserSGPRs += 4;
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return ArgInfo.PrivateSegmentBuffer.getRegister();
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}
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unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
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ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.DispatchPtr.getRegister();
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}
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unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
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ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.QueuePtr.getRegister();
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}
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unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
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ArgInfo.KernargSegmentPtr
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= ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.KernargSegmentPtr.getRegister();
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}
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unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
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ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.DispatchID.getRegister();
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}
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unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
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ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.FlatScratchInit.getRegister();
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}
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unsigned SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
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ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.ImplicitBufferPtr.getRegister();
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}
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static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
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for (unsigned I = 0; CSRegs[I]; ++I) {
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if (CSRegs[I] == Reg)
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return true;
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}
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return false;
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}
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/// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
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bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
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int FI) {
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std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
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// This has already been allocated.
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if (!SpillLanes.empty())
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return true;
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned WaveSize = ST.getWavefrontSize();
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unsigned Size = FrameInfo.getObjectSize(FI);
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assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
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assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
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int NumLanes = Size / 4;
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const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
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// Make sure to handle the case where a wide SGPR spill may span between two
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// VGPRs.
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for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
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unsigned LaneVGPR;
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unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
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if (VGPRIndex == 0) {
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LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
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if (LaneVGPR == AMDGPU::NoRegister) {
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// We have no VGPRs left for spilling SGPRs. Reset because we will not
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// partially spill the SGPR to VGPRs.
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SGPRToVGPRSpills.erase(FI);
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NumVGPRSpillLanes -= I;
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return false;
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}
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Optional<int> CSRSpillFI;
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if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
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isCalleeSavedReg(CSRegs, LaneVGPR)) {
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CSRSpillFI = FrameInfo.CreateSpillStackObject(4, 4);
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}
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SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineBasicBlock &BB : MF)
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BB.addLiveIn(LaneVGPR);
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} else {
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LaneVGPR = SpillVGPRs.back().VGPR;
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}
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SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
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}
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return true;
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}
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void SIMachineFunctionInfo::removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI) {
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for (auto &R : SGPRToVGPRSpills)
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MFI.RemoveStackObject(R.first);
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}
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/// \returns VGPR used for \p Dim' work item ID.
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unsigned SIMachineFunctionInfo::getWorkItemIDVGPR(unsigned Dim) const {
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switch (Dim) {
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case 0:
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assert(hasWorkItemIDX());
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return AMDGPU::VGPR0;
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case 1:
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assert(hasWorkItemIDY());
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return AMDGPU::VGPR1;
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case 2:
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assert(hasWorkItemIDZ());
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return AMDGPU::VGPR2;
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}
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llvm_unreachable("unexpected dimension");
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}
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MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
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assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
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return AMDGPU::SGPR0 + NumUserSGPRs;
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}
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MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
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return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
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}
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