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Benjamin Kramer 309124e0b1 [PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate 
I'm not even sure if this transform is ever worth it, but this at least
stops the bleeding.

llvm-svn: 322373
2018-01-12 15:03:24 +00:00
..
2004-11-29-ShrCrash.ll
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2004-11-30-shift-crash.ll
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2004-11-30-shr-var-crash.ll
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2004-12-12-ZeroSizeCommon.ll
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2005-01-14-SetSelectCrash.ll
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2005-01-14-UndefLong.ll
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2005-08-12-rlwimi-crash.ll
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2005-09-02-LegalizeDuplicatesCalls.ll
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2005-10-08-ArithmeticRotate.ll
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2005-11-30-vastart-crash.ll
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2006-01-11-darwin-fp-argument.ll
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2006-01-20-ShiftPartsCrash.ll
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2006-04-01-FloatDoubleExtend.ll
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2006-04-05-splat-ish.ll
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2006-04-19-vmaddfp-crash.ll
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2006-05-12-rlwimi-crash.ll
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2006-07-07-ComputeMaskedBits.ll
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2006-07-19-stwbrx-crash.ll
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2006-08-11-RetVector.ll
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2006-08-15-SelectionCrash.ll
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2006-09-28-shift_64.ll
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2006-10-13-Miscompile.ll
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2006-10-17-brcc-miscompile.ll
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2006-10-17-ppc64-alloca.ll
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2006-11-10-DAGCombineMiscompile.ll
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2006-11-29-AltivecFPSplat.ll
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2006-12-07-LargeAlloca.ll
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2006-12-07-SelectCrash.ll
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2007-01-04-ArgExtension.ll
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2007-01-15-AsmDialect.ll
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2007-01-29-lbrx-asm.ll
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2007-01-31-InlineAsmAddrMode.ll
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2007-02-16-AlignPacked.ll
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2007-02-16-InlineAsmNConstraint.ll
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2007-02-23-lr-saved-twice.ll
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2007-03-24-cntlzd.ll
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2007-03-30-SpillerCrash.ll
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2007-04-24-InlineAsm-I-Modifier.ll
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2007-04-30-InlineAsmEarlyClobber.ll
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2007-05-03-InlineAsm-S-Constraint.ll
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2007-05-14-InlineAsmSelectCrash.ll
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2007-05-22-tailmerge-3.ll
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2007-05-30-dagcombine-miscomp.ll
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2007-06-28-BCCISelBug.ll
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2007-08-04-CoalescerAssert.ll
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2007-09-04-AltivecDST.ll
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2007-09-07-LoadStoreIdxForms.ll
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2007-09-08-unaligned.ll
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2007-09-11-RegCoalescerAssert.ll
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2007-09-12-LiveIntervalsAssert.ll
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2007-10-16-InlineAsmFrameOffset.ll
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2007-10-18-PtrArithmetic.ll
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2007-10-21-LocalRegAllocAssert2.ll
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2007-10-21-LocalRegAllocAssert.ll
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2007-11-04-CoalescerCrash.ll
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2007-11-16-landingpad-split.ll
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2007-11-19-VectorSplitting.ll
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2008-02-05-LiveIntervalsAssert.ll
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2008-02-09-LocalRegAllocAssert.ll
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2008-03-05-RegScavengerAssert.ll
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2008-03-17-RegScavengerCrash.ll
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2008-03-18-RegScavengerAssert.ll
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2008-03-24-AddressRegImm.ll
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2008-03-24-CoalescerBug.ll
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2008-03-26-CoalescerBug.ll
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2008-04-10-LiveIntervalCrash.ll
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2008-04-16-CoalescerBug.ll
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2008-04-23-CoalescerCrash.ll
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2008-05-01-ppc_fp128.ll
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2008-06-19-LegalizerCrash.ll
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2008-06-21-F128LoadStore.ll
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2008-06-23-LiveVariablesCrash.ll
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2008-07-10-SplatMiscompile.ll
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2008-07-15-Bswap.ll
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2008-07-15-Fabs.ll
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2008-07-15-SignExtendInreg.ll
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2008-07-17-Fneg.ll
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2008-07-24-PPC64-CCBug.ll
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2008-09-12-CoalescerBug.ll
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2008-10-17-AsmMatchingOperands.ll
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2008-10-28-f128-i32.ll
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2008-10-28-UnprocessedNode.ll
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2008-10-31-PPCF128Libcalls.ll
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2008-12-02-LegalizeTypeAssert.ll
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2009-01-16-DeclareISelBug.ll
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2009-03-17-LSRBug.ll
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2009-05-28-LegalizeBRCC.ll
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2009-07-16-InlineAsm-M-Operand.ll
[CodeGen] Print external symbols as $symbol in both MIR and debug output
2017-12-14 10:02:58 +00:00
2009-08-17-inline-asm-addr-mode-breakage.ll
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2009-09-18-carrybit.ll
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2009-11-15-ProcImpDefsBug.ll
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2009-11-25-ImpDefBug.ll
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2010-02-04-EmptyGlobal.ll
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2010-02-12-saveCR.ll
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2010-03-09-indirect-call.ll
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2010-04-01-MachineCSEBug.ll
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2010-05-03-retaddr1.ll
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2010-10-11-Fast-Varargs.ll
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2010-12-18-PPCStackRefs.ll
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2011-12-05-NoSpillDupCR.ll
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2011-12-06-SpillAndRestoreCR.ll
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2011-12-08-DemandedBitsMiscompile.ll
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2012-09-16-TOC-entry-check.ll
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2012-10-11-dynalloc.ll
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2012-10-12-bitcast.ll
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2012-11-16-mischedcall.ll
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2013-05-15-preinc-fold.ll
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2013-07-01-PHIElimBug.ll
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2016-01-07-BranchWeightCrash.ll
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2016-04-16-ADD8TLS.ll
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2016-04-17-combine.ll
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2016-04-28-setjmp.ll
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a2-fp-basic.ll
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a2q-stackalign.ll
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a2q.ll
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aa-tbaa.ll
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aantidep-def-ec.mir
[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.
2018-01-10 00:56:48 +00:00
aantidep-inline-asm-use.ll
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add-fi.ll
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addc.ll
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addegluecrash.ll
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addi-licm.ll
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addi-reassoc.ll
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addisdtprelha-nonr3.mir
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addrfuncstr.ll
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aggressive-anti-dep-breaker-subreg.ll
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alias.ll
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align.ll
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allocate-r0.ll
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altivec-ord.ll
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and_add.ll
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and_sext.ll
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and_sra.ll
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and-branch.ll
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and-elim.ll
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and-imm.ll
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andc.ll
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anon_aggr.ll
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anyext_srl.ll
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arr-fp-arg-no-copy.ll
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ashr-neg1.ll
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asm-constraints.ll
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asm-dialect.ll
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asm-printer-topological-order.ll
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asm-Zy.ll
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asym-regclass-copy.ll
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atomic-1.ll
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atomic-2.ll
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atomic-minmax.ll
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Atomics-64.ll
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atomics-constant.ll
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atomics-fences.ll
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atomics-indexed.ll
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atomics-regression.ll
[PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP
2018-01-12 14:58:41 +00:00
atomics.ll
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available-externally.ll
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bdzlr.ll
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big-endian-actual-args.ll
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big-endian-call-result.ll
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big-endian-formal-args.ll
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bitcasts-direct-move.ll
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blockaddress.ll
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BoolRetToIntTest-2.ll
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BoolRetToIntTest.ll
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bperm.ll
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branch_coalesce.ll
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branch-hint.ll
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branch-opt.ll
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BreakableToken-reduced.ll
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bswap64.ll
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bswap-load-store.ll
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build-vector-tests.ll
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
2017-12-15 07:27:53 +00:00
buildvec_canonicalize.ll
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builtins-ppc-elf2-abi.ll
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builtins-ppc-p8vector.ll
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bv-pres-v8i1.ll
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bv-widen-undef.ll
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byval-agg-info.ll
[MachineOperand][MIR] Add isRenamable to MachineOperand.
2017-12-12 17:53:59 +00:00
byval-aliased.ll
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calls.ll
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can-lower-ret.ll
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cannonicalize-vector-shifts.ll
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cc.ll
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change-no-infs.ll
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cmp_elimination.ll
[PowerPC] fix a bug in redundant compare elimination
2017-12-20 05:18:19 +00:00
cmp-cmp.ll
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cmpb-ppc32.ll
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cmpb.ll
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coal-sections.ll
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coalesce-ext.ll
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code-align.ll
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combine_loads_from_build_pair.ll
Unbreak test relying on debug output after r321540.
2017-12-28 21:36:10 +00:00
combine-to-pre-index-store-crash.ll
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compare-duplicate.ll
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compare-simm.ll
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CompareEliminationSpillIssue.ll
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complex-return.ll
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constants-i64.ll
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constants.ll
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convert-rr-to-ri-instrs-out-of-range.mir
[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion
2017-12-29 12:22:27 +00:00
convert-rr-to-ri-instrs-R0-special-handling.mir
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
2017-12-15 07:27:53 +00:00
convert-rr-to-ri-instrs.mir
[PowerPC] Don't miscompile rotate+mask into an ANDIo if it can't recreate the immediate
2018-01-12 15:03:24 +00:00
copysignl.ll
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cr1eq-no-extra-moves.ll
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cr1eq.ll
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cr_spilling.ll
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cr-spills.ll
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crash.ll
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crbit-asm-disabled.ll
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crbit-asm.ll
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crbits.ll
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crsave.ll
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crypto_bifs.ll
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ctr-loop-tls-const.ll
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ctrloop-cpsgn.ll
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ctrloop-udivti3.ll
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ctrloops.ll
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cttz.ll
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dbg.ll
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DbgValueOtherTargets.test
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debuginfo-stackarg.ll
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delete-node.ll
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direct-move-profit.ll
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div-2.ll
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div-e-32.ll
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div-e-all.ll
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duplicate-returns-for-tailcall.ll
[PowerPC] fix a bug in TCO eligibility check
2017-12-30 08:09:04 +00:00
dyn-alloca-aligned.ll
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dyn-alloca-offset.ll
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e500-1.ll
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early-ret2.ll
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early-ret.ll
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ec-input.ll
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eh-dwarf-cfa.ll
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empty-functions.ll
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emptystruct.ll
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emutls_generic.ll
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eqv-andc-orc-nor.ll
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expand-contiguous-isel.ll
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expand-foldable-isel.ll
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expand-isel-1.mir
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expand-isel.ll
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ext-bool-trunc-repl.ll
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extra-toc-reg-deps.ll
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extsh.ll
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f32-to-i64.ll
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fabs.ll
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fast-isel-binary.ll
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fast-isel-br-const.ll
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fast-isel-call.ll
[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.
2017-12-18 19:21:56 +00:00
fast-isel-cmp-imm.ll
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fast-isel-const.ll
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fast-isel-ext.ll
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fast-isel-fcmp-nan.ll
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fma-ext.ll
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fma-mutate-duplicate-vreg.ll
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fma.ll
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fminnum.ll
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fnabs.ll
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fneg.ll
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fold-li.ll
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fold-zero.ll
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fp2int2fp-ppcfp128.ll
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fp64-to-int16.ll
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fp128-bitcast-after-operation.ll
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fp_to_uint.ll
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fp-branch.ll
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fp-int-conversions-direct-moves.ll
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fp-int-fp.ll
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fp-splat.ll
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fp-to-int-ext.ll
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fp-to-int-to-fp.ll
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fpcopy.ll
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frame-size.ll
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frameaddr.ll
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frounds.ll
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fsel.ll
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fsl-e500mc.ll
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fsl-e5500.ll
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fsqrt.ll
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func-addr-consts.ll
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func-addr.ll
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glob-comp-aa-crash.ll
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gpr-vsr-spill.ll
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hello-reloc.s
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hello.ll
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hidden-vis-2.ll
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hidden-vis.ll
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htm.ll
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i1-ext-fold.ll
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i1-to-double.ll
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i32-to-float.ll
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i64_fp_round.ll
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i64_fp.ll
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i64-to-float.ll
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i128-and-beyond.ll
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ia-mem-r0.ll
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ia-neg-const.ll
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iabs.ll
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ifcvt-forked-bug-2016-08-08.ll
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ifcvt.ll
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illegal-element-type.ll
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in-asm-f64-reg.ll
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indexed-load.ll
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indirect-hidden.ll
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indirectbr.ll
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inline-asm-s-modifier.ll
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inline-asm-scalar-to-vector-error.ll
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inlineasm-copy.ll
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inlineasm-i64-reg.ll
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int-fp-conv-0.ll
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int-fp-conv-1.ll
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inverted-bool-compares.ll
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isel-rc-nox0.ll
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isel.ll
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ispositive.ll
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itofp128.ll
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jaggedstructs.ll
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LargeAbsoluteAddr.ll
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lbz-from-ld-shift.ll
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lbzux.ll
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ld-st-upd.ll
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ldtoc-inv.ll
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lha.ll
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licm-remat.ll
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
2017-12-13 14:47:35 +00:00
licm-tocReg.ll
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lit.local.cfg
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livephysregs.mir
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load-constant-addr.ll
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load-shift-combine.ll
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load-two-flts.ll
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load-v4i8-improved.ll
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logic-ops-on-compares.ll
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long-compare.ll
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longcall.ll
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longdbl-truncate.ll
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loop-data-prefetch-inner.ll
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loop-data-prefetch.ll
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loop-prep-all.ll
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lsa.ll
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lsr-postinc-pos.ll
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lxv-aligned-stack-slots.ll
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lxvw4x-bug.ll
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machine-combiner.ll
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mask64.ll
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mature-mc-support.ll
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mc-instrlat.ll
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mcm-1.ll
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mcm-2.ll
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mcm-default.ll
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mcm-obj-2.ll
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mcm-obj.ll
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mcount-insertion.ll
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MCSE-caller-preserved-reg.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
mem_update.ll
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mem-rr-addr-mode.ll
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memcmp.ll
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memcmpIR.ll
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memCmpUsedInZeroEqualityComparison.ll
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memcpy_dereferenceable.ll
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memcpy-vec.ll
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memset-nc-le.ll
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memset-nc.ll
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merge_stores_dereferenceable.ll
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merge-st-chain-op.ll
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mftb.ll
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misched-inorder-latency.ll
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misched.ll
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MMO-flags-assertion.ll
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mtvsrdd.ll
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mul-with-overflow.ll
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mulhs.ll
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mulli64.ll
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mult-alt-generic-powerpc64.ll
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mult-alt-generic-powerpc.ll
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multi-return.ll
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named-reg-alloc-r0.ll
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named-reg-alloc-r1-64.ll
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neg.ll
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negate-i1.ll
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negctr.ll
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no-dead-strip.ll
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no-dup-spill-fp.ll
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no-ext-with-count-zeros.ll
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no-extra-fp-conv-ldst.ll
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no-pref-jumps.ll
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no-rlwimi-trivial-commute.mir
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non-simple-args-intrin.ll
[PowerPC] Can not assume an intrinsic argument is a simple type.
2018-01-09 03:03:41 +00:00
novrsave.ll
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opt-cmp-inst-cr0-live.ll
[CodeGen] Don't print register classes in -debug output
2018-01-09 15:39:44 +00:00
opt-li-add-to-addi.ll
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opt-sub-inst-cr0-live.mir
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optcmp.ll
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optnone-crbits-i1-ret.ll
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ori_imm32.ll
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p8-isel-sched.ll
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p8-scalar_vector_conversions.ll
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p8altivec-shuffles-pred.ll
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p9-vector-compares-and-counts.ll
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p9-vinsert-vextract.ll
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p9-xxinsertw-xxextractuw.ll
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peephole-align.ll
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pie.ll
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pip-inner.ll
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popcnt.ll
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post-ra-ec.ll
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power9-moves-and-splats.ll
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ppc32-align-long-double-sf.ll
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ppc32-constant-BE-ppcf128.ll
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ppc32-cyclecounter.ll
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ppc32-lshrti3.ll
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ppc32-skip-regs.ll
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ppc32-vacopy.ll
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ppc64-32bit-addic.ll
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ppc64-abi-extend.ll
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ppc64-align-long-double.ll
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ppc64-altivec-abi.ll
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ppc64-anyregcc-crash.ll
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ppc64-blnop.ll
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ppc64-byval-align.ll
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ppc64-calls.ll
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ppc64-crash.ll
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ppc64-cyclecounter.ll
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ppc64-elf-abi.ll
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ppc64-fastcc-fast-isel.ll
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ppc64-fastcc.ll
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ppc64-func-desc-hoist.ll
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ppc64-gep-opt.ll
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ppc64-get-cache-line-size.ll
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ppc64-linux-func-size.ll
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ppc64-patchpoint.ll
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ppc64-pre-inc-no-extra-phi.ll
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ppc64-prefetch.ll
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ppc64-r2-alloc.ll
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ppc64-sibcall-shrinkwrap.ll
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ppc64-sibcall.ll
[PowerPC] fix a bug in TCO eligibility check
2017-12-30 08:09:04 +00:00
ppc64-smallarg.ll
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ppc64-stackmap.ll
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ppc-ctr-dead-code.ll
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ppc-empty-fs.ll
…
ppc-prologue.ll
…
ppc-redzone-alignment-bug.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
ppc-shrink-wrapping.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
ppc-vaarg-agg.ll
…
ppcf128-1-opt.ll
…
ppcf128-1.ll
…
ppcf128-2.ll
…
ppcf128-3.ll
…
ppcf128-4.ll
…
ppcf128-endian.ll
…
ppcf128sf.ll
…
ppcsoftops.ll
…
pr3711_widen_bit.ll
…
pr12757.ll
…
pr13641.ll
…
pr13891.ll
…
pr15031.ll
…
pr15359.ll
…
pr15630.ll
…
pr15632.ll
…
pr16556-2.ll
…
pr16556.ll
…
pr16573.ll
…
pr17168.ll
…
pr17354.ll
…
pr18663-2.ll
…
pr18663.ll
…
pr20442.ll
…
pr22711.ll
…
pr24216.ll
…
pr24546.ll
…
pr24636.ll
…
pr25157-peephole.ll
…
pr25157.ll
…
pr26180.ll
…
pr26193.ll
…
pr26356.ll
…
pr26378.ll
…
pr26381.ll
…
pr26617.ll
…
pr26690.ll
…
pr27078.ll
…
pr27350.ll
…
pr28130.ll
…
pr28630.ll
…
pr30451.ll
…
pr30640.ll
…
pr30663.ll
…
pr30715.ll
…
pr31144.ll
…
pr32063.ll
…
pr32140.ll
…
pr33093.ll
…
pr35688.ll
[PowerPC] Fix for PR35688 - handle out-of-range values for r+r to r+i conversion
2017-12-29 12:22:27 +00:00
PR3488.ll
…
PR33636.ll
…
PR33671.ll
…
PR35812-neg-cmpxchg.ll
[PowerPC] Zero-extend the compare operand for ATOMIC_CMP_SWAP
2018-01-12 14:58:41 +00:00
preemption.ll
…
preinc-ld-sel-crash.ll
…
preincprep-invoke.ll
…
preincprep-nontrans-crash.ll
…
private.ll
…
pwr3-6x.ll
…
pwr7-gt-nop.ll
…
pzero-fp-xored.ll
…
qpx-bv-sint.ll
…
qpx-bv.ll
…
qpx-func-clobber.ll
…
qpx-load-splat.ll
…
qpx-load.ll
…
qpx-recipest.ll
…
qpx-rounding-ops.ll
…
qpx-s-load.ll
…
qpx-s-sel.ll
…
qpx-s-store.ll
…
qpx-sel.ll
…
qpx-split-vsetcc.ll
…
qpx-store.ll
…
qpx-unal-cons-lds.ll
…
qpx-unalperm.ll
…
quadint-return.ll
…
r31.ll
…
recipest.ll
…
reg-coalesce-simple.ll
…
reg-names.ll
…
reloc-align.ll
…
remap-crash.ll
…
remat-imm.ll
…
remove-redundant-moves.ll
…
remove-redundant-toc-saves.ll
…
resolvefi-basereg.ll
…
resolvefi-disp.ll
…
restore-r30.ll
…
retaddr2.ll
…
retaddr.ll
…
return-val-i128.ll
…
rlwimi2.ll
…
rlwimi3.ll
…
rlwimi-and-or-bits.ll
…
rlwimi-and.ll
…
rlwimi-commute.ll
…
rlwimi-dyn-and.ll
…
rlwimi-keep-rsh.ll
…
rlwimi.ll
…
rlwinm2.ll
…
rlwinm-zero-ext.ll
…
rlwinm.ll
…
rm-zext.ll
…
rotl-2.ll
…
rotl-64.ll
…
rotl-rotr-crash.ll
…
rotl.ll
…
rounding-ops.ll
…
rs-undef-use.ll
…
s000-alias-misched.ll
…
save-bp.ll
…
save-cr-ppc32svr4.ll
…
save-crbp-ppc32svr4.ll
…
scavenging.mir
…
sdag-ppcf128.ll
…
sdiv-pow2.ll
…
sections.ll
…
select_const.ll
…
select_lt0.ll
…
select-addrRegRegOnly.ll
…
select-cc.ll
…
select-i1-vs-i1.ll
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
2017-12-13 14:47:35 +00:00
selectiondag-extload-computeknownbits.ll
…
selectiondag-sextload.ll
…
set0-v8i16.ll
…
setcc_no_zext.ll
…
setcc-logic.ll
[PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.
2017-12-18 19:21:56 +00:00
setcc-to-sub.ll
…
setcclike-or-comb.ll
…
seteq-0.ll
…
shift128.ll
…
shift_mask.ll
…
shift-cmp.ll
…
shl_elim.ll
…
shl_sext.ll
…
sign_ext_inreg1.ll
…
simplifyConstCmpToISEL.ll
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
2017-12-15 07:27:53 +00:00
sj-ctr-loop.ll
…
sjlj_no0x.ll
…
sjlj.ll
…
small-arguments.ll
…
spill-nor0.ll
…
splat-bug.ll
…
splat-larger-types-as-v16i8.ll
…
split-index-tc.ll
…
srl-mask.ll
…
stack-no-redzone.ll
…
stack-protector.ll
…
stack-realign.ll
…
stackmap-frame-setup.ll
…
stacksize.ll
…
std-unal-fi.ll
…
stdux-constuse.ll
…
stfiwx-2.ll
…
stfiwx.ll
…
store-constant.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
store-load-fwd.ll
…
store-update.ll
…
structsinmem.ll
…
structsinregs.ll
…
stubs.ll
…
stwu8.ll
…
stwu-gta.ll
…
stwux.ll
…
sub-bv-types.ll
…
subc.ll
…
subreg-postra-2.ll
…
subreg-postra.ll
…
subtract_from_imm.ll
…
svr4-redzone.ll
…
swaps-le-1.ll
…
swaps-le-2.ll
…
swaps-le-3.ll
…
swaps-le-4.ll
…
swaps-le-5.ll
…
swaps-le-6.ll
…
swaps-le-7.ll
…
tail-dup-analyzable-fallthrough.ll
…
tail-dup-branch-to-fallthrough.ll
…
tail-dup-break-cfg.ll
…
tail-dup-layout.ll
[PowerPC] MachineSSA pass to reduce the number of CR-logical operations
2017-12-13 14:47:35 +00:00
tailcall1-64.ll
…
tailcall1.ll
…
tailcall-string-rvo.ll
…
tailcallpic1.ll
…
testBitReverse.ll
…
testComparesi32gtu.ll
…
testComparesi32leu.ll
…
testComparesi32ltu.ll
…
testComparesieqsc.ll
…
testComparesieqsi.ll
…
testComparesieqsll.ll
…
testComparesieqss.ll
…
testComparesiequc.ll
…
testComparesiequi.ll
…
testComparesiequll.ll
…
testComparesiequs.ll
…
testComparesigesc.ll
…
testComparesigesi.ll
…
testComparesigesll.ll
…
testComparesigess.ll
…
testComparesigeuc.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesigeui.ll
…
testComparesigeull.ll
…
testComparesigeus.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesigtsc.ll
…
testComparesigtsi.ll
…
testComparesigtsll.ll
…
testComparesigtss.ll
…
testComparesigtuc.ll
…
testComparesigtui.ll
…
testComparesigtus.ll
…
testComparesilesc.ll
…
testComparesilesi.ll
…
testComparesilesll.ll
…
testComparesiless.ll
…
testComparesileuc.ll
…
testComparesileui.ll
…
testComparesileull.ll
…
testComparesileus.ll
…
testComparesiltsc.ll
…
testComparesiltsi.ll
…
testComparesiltsll.ll
…
testComparesiltss.ll
…
testComparesiltuc.ll
…
testComparesiltui.ll
…
testComparesiltus.ll
…
testComparesinesc.ll
…
testComparesinesi.ll
…
testComparesinesll.ll
…
testComparesiness.ll
…
testComparesineuc.ll
…
testComparesineui.ll
…
testComparesineull.ll
…
testComparesineus.ll
…
testCompareslleqsc.ll
…
testCompareslleqsi.ll
…
testCompareslleqsll.ll
…
testCompareslleqss.ll
…
testComparesllequc.ll
…
testComparesllequi.ll
…
testComparesllequll.ll
…
testComparesllequs.ll
…
testComparesllgesc.ll
…
testComparesllgesi.ll
…
testComparesllgesll.ll
…
testComparesllgess.ll
…
testComparesllgeuc.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesllgeui.ll
…
testComparesllgeull.ll
…
testComparesllgeus.ll
[PowerPC] Follow-up to r318436 to get the missed CSE opportunities
2017-12-12 12:09:34 +00:00
testComparesllgtsll.ll
…
testComparesllgtuc.ll
…
testComparesllgtui.ll
…
testComparesllgtus.ll
…
testCompareslllesc.ll
…
testCompareslllesi.ll
…
testCompareslllesll.ll
…
testComparesllless.ll
…
testComparesllleuc.ll
…
testComparesllleui.ll
…
testComparesllleull.ll
…
testComparesllleus.ll
…
testComparesllltsll.ll
…
testComparesllltuc.ll
…
testComparesllltui.ll
…
testComparesllltus.ll
…
testComparesllnesll.ll
…
testComparesllneull.ll
…
thread-pointer.ll
…
tls_get_addr_clobbers.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
tls_get_addr_fence1.mir
…
tls_get_addr_fence2.mir
…
tls_get_addr_stackframe.ll
…
tls-cse.ll
…
tls-pic.ll
…
tls-store2.ll
…
tls.ll
…
toc-load-sched-bug.ll
…
trampoline.ll
…
uint-to-ppcfp128-crash.ll
[PowerPC] Fix parest build failure in SPEC2017.
2017-12-21 15:42:50 +00:00
unal4-std.ll
…
unal-altivec2.ll
…
unal-altivec-wint.ll
…
unal-altivec.ll
…
unal-vec-ldst.ll
…
unal-vec-negarith.ll
…
unaligned.ll
[PowerPC] Convert r+r instructions to r+i (pre and post RA)
2017-12-15 07:27:53 +00:00
unsafe-math.ll
…
unwind-dw2-g.ll
…
unwind-dw2.ll
…
vaddsplat.ll
…
varargs-struct-float.ll
…
varargs.ll
…
variable_elem_vec_extracts.ll
[SelectionDAG] Reverse the order of operands in the ISD::ADD created by TargetLowering::getVectorElementPointer so that the FrameIndex is on the left.
2017-12-22 17:18:13 +00:00
vcmp-fold.ll
…
vec_abs.ll
…
vec_absd.ll
…
vec_add_sub_doubleword.ll
…
vec_add_sub_quadword.ll
…
vec_auto_constant.ll
…
vec_br_cmp.ll
…
vec_buildvector_loadstore.ll
…
vec_call.ll
…
vec_clz.ll
…
vec_cmp.ll
…
vec_cmpd.ll
…
vec_constants.ll
…
vec_conv.ll
…
vec_extload.ll
…
vec_extract_p9_2.ll
…
vec_extract_p9.ll
…
vec_fmuladd.ll
…
vec_fneg.ll
…
vec_insert.ll
…
vec_int_ext.ll
…
vec_mergeow.ll
…
vec_minmax.ll
…
vec_misaligned.ll
…
vec_mul_even_odd.ll
…
vec_mul.ll
…
vec_perf_shuffle.ll
…
vec_popcnt.ll
…
vec_revb.ll
…
vec_rotate_shift.ll
…
vec_rounding.ll
…
vec_select.ll
…
vec_shift.ll
…
vec_shuffle_le.ll
…
vec_shuffle_p8vector_le.ll
…
vec_shuffle_p8vector.ll
…
vec_shuffle.ll
…
vec_sldwi.ll
…
vec_splat_constant.ll
…
vec_splat.ll
…
vec_sqrt.ll
…
vec_urem_const.ll
…
vec_veqv_vnand_vorc.ll
…
vec_vrsave.ll
…
vec_xxpermdi.ll
…
vec_zero.ll
…
vec-abi-align.ll
…
vec-asm-disabled.ll
…
vector-identity-shuffle.ll
…
vector-merge-store-fp-constants.ll
…
vector.ll
…
vperm-instcombine.ll
…
vperm-lowering.ll
…
vrsave-spill.ll
…
vrspill.ll
…
vsel-prom.ll
…
vselect-constants.ll
…
vsx_insert_extract_le.ll
…
vsx_scalar_ld_st.ll
…
vsx_shuffle_le.ll
…
vsx-args.ll
…
VSX-DForm-Scalars.ll
…
vsx-div.ll
…
vsx-elementary-arith.ll
…
vsx-fma-m.ll
…
vsx-fma-mutate-trivial-copy.ll
…
vsx-fma-mutate-undef.ll
…
vsx-fma-sp.ll
…
vsx-infl-copy1.ll
…
vsx-infl-copy2.ll
…
vsx-ldst-builtin-le.ll
…
vsx-ldst.ll
…
vsx-minmax.ll
…
vsx-p8.ll
…
vsx-p9.ll
…
vsx-partword-int-loads-and-stores.ll
…
vsx-recip-est.ll
…
vsx-self-copy.ll
…
vsx-spill-norwstore.ll
…
vsx-spill.ll
…
vsx-vec-spill.ll
…
vsx-word-splats.ll
…
VSX-XForm-Scalars.ll
…
vsx.ll
…
vsxD-Form-spills.ll
Revert "[PowerPC] Manually schedule the prologue and epilogue"
2018-01-12 13:12:49 +00:00
vtable-reloc.ll
…
weak_def_can_be_hidden.ll
…
xray-attribute-instrumentation.ll
…
xray-conditional-return.ll
…
xray-ret-is-terminator.ll
…
xray-tail-call-hidden.ll
…
xray-tail-call-sled.ll
…
xvcmpeqdp-v2f64.ll
…
xxleqv_xxlnand_xxlorc.ll
…
zero-not-run.ll
…
zext-and-cmp.ll
…
zext-bitperm.ll
…
zext-free.ll
…