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clang-p2996/llvm/test/CodeGen/RISCV
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Luís Marques 89840380d5 [RISCV][NFC] Add more tests for 32-bit constant materialization 
The existing tests were mostly for 64-bit constants.

Differential Revision: https://reviews.llvm.org/D83210
2020-10-22 11:36:34 +01:00
..
GlobalISel
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intrinsics
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add-before-shl.ll
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add-imm.ll
[RISCV] optimize addition with a pair of (addi imm)
2020-07-07 18:57:28 -07:00
addc-adde-sube-subc.ll
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addcarry.ll
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addimm-mulimm.ll
[RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation
2020-07-10 18:33:12 -07:00
align.ll
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alloca.ll
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alu8.ll
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alu16.ll
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alu32.ll
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alu64.ll
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analyze-branch.ll
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arith-with-overflow.ll
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atomic-cmpxchg-flag.ll
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atomic-cmpxchg.ll
[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
2020-04-01 15:51:26 +01:00
atomic-fence.ll
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atomic-load-store.ll
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atomic-rmw.ll
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
2020-08-27 10:32:22 +01:00
attributes.ll
[RISCV] ELF attribute section for RISC-V.
2020-03-31 16:16:19 +08:00
bare-select.ll
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blockaddress.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
branch-relaxation.ll
[RISCV] Indirect branch generation in position independent code
2020-08-17 13:09:26 +01:00
branch.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
bswap-ctlz-cttz-ctpop.ll
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byval.ll
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callee-saved-fpr32s.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
callee-saved-fpr64s.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
callee-saved-gprs.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
calling-conv-ilp32-ilp32f-common.ll
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
2020-08-27 10:32:22 +01:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
2020-08-27 10:32:22 +01:00
calling-conv-ilp32.ll
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calling-conv-ilp32d.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
calling-conv-lp64-lp64f-common.ll
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calling-conv-lp64-lp64f-lp64d-common.ll
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
2020-08-27 10:32:22 +01:00
calling-conv-lp64.ll
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calling-conv-rv32f-ilp32.ll
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calling-conv-sext-zext.ll
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calls.ll
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cmp-bool.ll
[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
2020-07-15 07:34:22 +00:00
codemodel-lowering.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
compress-float.ll
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compress-inline-asm.ll
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compress.ll
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copysign-casts.ll
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disable-tail-calls.ll
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disjoint.ll
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div.ll
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double-arith.ll
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
double-bitmanip-dagcombines.ll
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double-br-fcmp.ll
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double-calling-conv.ll
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double-convert.ll
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double-fcmp.ll
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double-frem.ll
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double-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
double-intrinsics.ll
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double-isnan.ll
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
double-mem.ll
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double-previous-failure.ll
[RISCV] Implement Hooks to avoid chaining SELECT
2020-07-01 11:56:31 +01:00
double-select-fcmp.ll
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double-stack-spill-restore.ll
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dwarf-eh.ll
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exception-pointer-register.ll
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fastcc-float.ll
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fastcc-int.ll
…
fixups-diff.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
fixups-relax-diff.ll
[llvm-readobj] Update tests because of changes in llvm-readobj behavior
2020-07-20 10:39:04 +01:00
float-arith.ll
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
float-bit-preserving-dagcombines.ll
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float-bitmanip-dagcombines.ll
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float-br-fcmp.ll
[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
2020-03-20 09:42:24 +00:00
float-convert.ll
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float-fcmp.ll
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float-frem.ll
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float-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
float-intrinsics.ll
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float-isnan.ll
[RISCV] Add patterns for checking isnan
2020-05-02 15:01:04 +01:00
float-mem.ll
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float-select-fcmp.ll
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flt-rounds.ll
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fold-addi-loadstore.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
fp16-promote.ll
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fp128.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
fp-imm.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
frame-info.ll
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frame.ll
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frameaddr-returnaddr.ll
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get-register-invalid.ll
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get-register-noreserve.ll
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get-register-reserve.ll
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get-setcc-result-type.ll
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hoist-global-addr-base.ll
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i32-icmp.ll
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imm-cse.ll
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imm.ll
[RISCV][NFC] Add more tests for 32-bit constant materialization
2020-10-22 11:36:34 +01:00
indirectbr.ll
[RISCV] Fix inaccurate annotations on PseudoBRIND
2020-08-21 11:38:42 +01:00
init-array.ll
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inline-asm-abi-names.ll
[MC][RISCV] Set UseIntegratedAssembler to true
2020-07-12 21:04:48 -07:00
inline-asm-clobbers.ll
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inline-asm-d-abi-names.ll
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inline-asm-d-constraint-f.ll
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inline-asm-f-abi-names.ll
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inline-asm-f-constraint-f.ll
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inline-asm-i-constraint-i1.ll
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inline-asm-invalid.ll
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inline-asm.ll
[MC][RISCV] Set UseIntegratedAssembler to true
2020-07-12 21:04:48 -07:00
interrupt-attr-args-error.ll
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interrupt-attr-callee.ll
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interrupt-attr-invalid.ll
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interrupt-attr-nocall.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
interrupt-attr-ret-error.ll
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interrupt-attr.ll
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jumptable.ll
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large-stack.ll
[MC][RISCV] Set UseIntegratedAssembler to true
2020-07-12 21:04:48 -07:00
legalize-fneg.ll
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lit.local.cfg
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lsr-legaladdimm.ll
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machineoutliner.mir
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mattr-invalid-combination.ll
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mem64.ll
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mem.ll
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mir-target-flags.ll
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
module-target-abi2.ll
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module-target-abi.ll
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mul.ll
[RISCV] Optimize multiplication by constant
2020-07-07 18:50:24 -07:00
musttail-call.ll
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nomerge.ll
Add NoMerge MIFlag to avoid MIR branch folding
2020-05-29 12:31:06 -07:00
option-nopic.ll
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
option-norelax.ll
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option-norvc.ll
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option-pic.ll
[RISCV][AsmParser] Implement .option (no)pic
2020-04-17 12:08:30 +00:00
option-relax.ll
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option-rvc.ll
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pic-models.ll
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
pr40333.ll
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prefetch.ll
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readcyclecounter.ll
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rem.ll
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remat.ll
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reserved-reg-errors.ll
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reserved-regs.ll
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rotl-rotr.ll
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rv32e.ll
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rv32i-rv64i-float-double.ll
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rv32Zbb.ll
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions
2020-07-15 12:19:34 +01:00
rv32Zbbp.ll
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
rv32Zbp.ll
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions
2020-07-15 12:19:34 +01:00
rv32Zbs.ll
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions
2020-07-15 12:19:34 +01:00
rv32Zbt.ll
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
rv64-large-stack.ll
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rv64d-double-convert.ll
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rv64f-float-convert.ll
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rv64i-complex-float.ll
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rv64i-exhaustive-w-insts.ll
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rv64i-single-softfloat.ll
[RISCV64] Emit correct lib call for fp(float/double) to ui/si
2020-06-18 19:34:16 +05:30
rv64i-tricky-shifts.ll
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rv64i-w-insts-legalization.ll
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rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
rv64Zbb.ll
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions
2020-07-15 12:19:34 +01:00
rv64Zbbp.ll
[SelectionDAG] Better legalization for FSHL and FSHR
2020-08-21 10:32:49 +01:00
rv64Zbp.ll
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions
2020-07-15 12:19:34 +01:00
rv64Zbs.ll
[RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions
2020-07-15 12:19:34 +01:00
rv64Zbt.ll
[DAG][ARM][MIPS][RISCV] Improve funnel shift promotion to use 'double shift' patterns
2020-10-12 14:11:02 +01:00
saverestore.ll
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sdata-limit-0.ll
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sdata-limit-4.ll
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sdata-limit-8.ll
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sdata-local-sym.ll
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select-and.ll
[RISCV] Implement Hooks to avoid chaining SELECT
2020-07-01 11:56:31 +01:00
select-cc.ll
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select-const.ll
[RISCV] Support Constant Pools in Load/Store Peephole
2020-05-11 19:20:38 +01:00
select-optimize-multiple.ll
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select-optimize-multiple.mir
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
select-or.ll
[RISCV] Implement Hooks to avoid chaining SELECT
2020-07-01 11:56:31 +01:00
setcc-logic.ll
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sext-zext-trunc.ll
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shadowcallstack.ll
[RISCV] Support Shadow Call Stack
2020-09-17 16:02:35 -07:00
shift-masked-shamt.ll
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shifts.ll
…
shrinkwrap.ll
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split-offsets.ll
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split-sp-adjust.ll
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srem-lkk.ll
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srem-vector-lkk.ll
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stack-realignment-with-variable-sized-objects.ll
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stack-realignment.ll
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stack-store-check.ll
[RISCV] Fix isStoreToStackSlot
2020-07-14 12:36:42 +00:00
subtarget-features-std-ext.ll
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tail-calls.ll
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target-abi-invalid.ll
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target-abi-valid.ll
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thread-pointer.ll
[RISCV] Support llvm.thread.pointer
2020-03-27 17:30:12 -07:00
tls-models.ll
Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
2020-07-14 11:15:01 +01:00
umulo-128-legalisation-lowering.ll
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urem-lkk.ll
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urem-vector-lkk.ll
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vararg.ll
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
2020-08-27 10:32:22 +01:00
verify-instr.mir
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wide-mem.ll
[RISCV] Fold ADDIs into load/stores with nonzero offsets
2020-07-06 17:32:57 +01:00
zext-with-load-is-free.ll
[RISCV] Implement Hooks to avoid chaining SELECT
2020-07-01 11:56:31 +01:00