Sanjay Patel 48a23bccf3 [VectorCombine] limit load+insert transform to one-use ...

As discussed in:
https://llvm.org/PR47558
...there are several potential fixes/follow-ups visible
in the test case, but this is the quickest and safest
fix of the perf regression.

2020-09-17 14:29:15 -04:00

..

extract-binop.ll

[VectorCombine] add/use pass-level IRBuilder

2020-06-22 09:01:29 -04:00

extract-cmp-binop.ll

[VectorCombine] try to form vector compare and binop to eliminate scalar ops

2020-06-29 10:38:52 -04:00

extract-cmp.ll

[VectorCombine] improve IR debugging by providing/salvaging value names

2020-06-22 08:35:47 -04:00

insert-binop-with-constant.ll

[VectorCombine] scalarizeBinop - support an all-constant src vector operand

2020-06-09 19:02:05 +01:00

insert-binop.ll

…

lit.local.cfg

…

load.ll

[VectorCombine] limit load+insert transform to one-use

2020-09-17 14:29:15 -04:00

no-sse.ll

[VectorCombine] early exit if target has no vector registers

2020-08-12 09:22:31 -04:00

scalarize-cmp.ll

[VectorCombine] fix assert for type of compare operand

2020-06-20 15:20:17 -04:00

shuffle.ll

[VectorCombine] add helper to replace uses and rename

2020-06-22 09:58:49 -04:00