9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
31 lines
1.5 KiB
LLVM
31 lines
1.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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declare float @llvm.amdgcn.cubeid(float, float, float) #0
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declare float @llvm.amdgcn.cubesc(float, float, float) #0
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declare float @llvm.amdgcn.cubetc(float, float, float) #0
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declare float @llvm.amdgcn.cubema(float, float, float) #0
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; GCN-LABEL: {{^}}cube:
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; GCN-DAG: v_cubeid_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: v_cubesc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: v_cubetc_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN-DAG: v_cubema_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: _store_dwordx4
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define amdgpu_kernel void @cube(ptr addrspace(1) %out, float %a, float %b, float %c) #1 {
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%cubeid = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
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%cubesc = call float @llvm.amdgcn.cubesc(float %a, float %b, float %c)
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%cubetc = call float @llvm.amdgcn.cubetc(float %a, float %b, float %c)
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%cubema = call float @llvm.amdgcn.cubema(float %a, float %b, float %c)
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%vec0 = insertelement <4 x float> undef, float %cubeid, i32 0
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%vec1 = insertelement <4 x float> %vec0, float %cubesc, i32 1
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%vec2 = insertelement <4 x float> %vec1, float %cubetc, i32 2
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%vec3 = insertelement <4 x float> %vec2, float %cubema, i32 3
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store <4 x float> %vec3, ptr addrspace(1) %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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