Files
clang-p2996/llvm/test/CodeGen/AMDGPU/missing-store.ll
Fangrui Song 9e9907f1cf [AMDGPU,test] Change llc -march= to -mtriple= (#75982)
Similar to 806761a762.

For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.

Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.

This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:

```
  LLVM :: CodeGen/AMDGPU/fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fabs.ll
  LLVM :: CodeGen/AMDGPU/floor.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
  LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
  LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
  LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
2024-01-16 21:54:58 -08:00

30 lines
1.1 KiB
LLVM

; RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
@ptr_load = addrspace(3) global ptr addrspace(4) undef, align 8
; Make sure when the load from %ptr2 is folded the chain isn't lost,
; resulting in losing the store to gptr
; FUNC-LABEL: {{^}}missing_store_reduced:
; SI: s_load_dwordx4
; SI-DAG: ds_read_b64
; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; SI-DAG: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; SI-DAG: s_load_dword s{{[0-9]+}}, s[[[PTR_LO]]:[[PTR_HI]]]
; SI-DAG: buffer_store_dword
; SI-DAG: buffer_store_dword
; SI: s_endpgm
define amdgpu_kernel void @missing_store_reduced(ptr addrspace(1) %out, ptr addrspace(1) %gptr) #0 {
%ptr0 = load ptr addrspace(4), ptr addrspace(3) @ptr_load, align 8
%ptr2 = getelementptr inbounds i32, ptr addrspace(4) %ptr0, i64 2
store i32 99, ptr addrspace(1) %gptr, align 4
%tmp2 = load i32, ptr addrspace(4) %ptr2, align 4
store i32 %tmp2, ptr addrspace(1) %out, align 4
ret void
}
attributes #0 = { nounwind }