f972e4d343
* Placing 'G' before 'M' (SHF_MERGE) can be misleading as the sh_entsize argument goes before the section group name, if a reader doesn't know that the order of extra arguments is not affected by the order of flags. * 'a', 'w', and 'x' indicate basic permission-related flags. Separating them with 'G' is kinda ugly. Simplify code and move 'G' after 'o'. The new output is more similar to GCC.
91 lines
3.0 KiB
LLVM
91 lines
3.0 KiB
LLVM
; RUN: llc -mtriple x86_64 < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-pc-linux -use-ctors < %s | FileCheck --check-prefix=CTOR %s
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; RUN: llc -mtriple x86_64-unknown-freebsd -use-ctors < %s | FileCheck --check-prefix=CTOR %s
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; RUN: llc -mtriple x86_64-pc-solaris2.11 -use-ctors < %s | FileCheck --check-prefix=CTOR %s
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; RUN: llc -mtriple x86_64-pc-linux < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-unknown-freebsd < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-pc-solaris2.11 < %s | FileCheck --check-prefix=INIT-ARRAY %s
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; RUN: llc -mtriple x86_64-unknown-nacl < %s | FileCheck --check-prefix=NACL %s
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; RUN: llc -mtriple i586-intel-elfiamcu -use-ctors < %s | FileCheck %s --check-prefix=MCU-CTORS
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; RUN: llc -mtriple i586-intel-elfiamcu < %s | FileCheck %s --check-prefix=MCU-INIT-ARRAY
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; RUN: llc -mtriple x86_64-win32-gnu < %s | FileCheck --check-prefix=COFF-CTOR %s
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@llvm.global_ctors = appending global [5 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @f, ptr null}, { i32, ptr, ptr } { i32 15, ptr @g, ptr @v }, { i32, ptr, ptr } { i32 55555, ptr @h, ptr @v }, { i32, ptr, ptr } { i32 65535, ptr @i, ptr null }, { i32, ptr, ptr } { i32 65535, ptr @j, ptr null }]
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@v = weak_odr global i8 0
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define void @f() {
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entry:
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ret void
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}
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define void @g() {
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entry:
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ret void
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}
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define void @h() {
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entry:
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ret void
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}
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define void @i() {
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entry:
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ret void
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}
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define void @j() {
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entry:
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ret void
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}
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; CTOR: .section .ctors,"aw",@progbits
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; CTOR-NEXT: .p2align 3
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; CTOR-NEXT: .quad j
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; CTOR-NEXT: .quad i
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; CTOR-NEXT: .quad f
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; CTOR-NEXT: .section .ctors.09980,"awG",@progbits,v,comdat
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; CTOR-NEXT: .p2align 3
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; CTOR-NEXT: .quad h
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; CTOR-NEXT: .section .ctors.65520,"awG",@progbits,v,comdat
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; CTOR-NEXT: .p2align 3
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; CTOR-NEXT: .quad g
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; INIT-ARRAY: .section .init_array.15,"awG",@init_array,v,comdat
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; INIT-ARRAY-NEXT: .p2align 3
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; INIT-ARRAY-NEXT: .quad g
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; INIT-ARRAY-NEXT: .section .init_array.55555,"awG",@init_array,v,comdat
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; INIT-ARRAY-NEXT: .p2align 3
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; INIT-ARRAY-NEXT: .quad h
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; INIT-ARRAY-NEXT: .section .init_array,"aw",@init_array
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; INIT-ARRAY-NEXT: .p2align 3
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; INIT-ARRAY-NEXT: .quad f
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; INIT-ARRAY-NEXT: .quad i
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; INIT-ARRAY-NEXT: .quad j
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; NACL: .section .init_array.15,"awG",@init_array,v,comdat
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; NACL-NEXT: .p2align 2
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; NACL-NEXT: .long g
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; NACL-NEXT: .section .init_array.55555,"awG",@init_array,v,comdat
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; NACL-NEXT: .p2align 2
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; NACL-NEXT: .long h
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; NACL-NEXT: .section .init_array,"aw",@init_array
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; NACL-NEXT: .p2align 2
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; NACL-NEXT: .long f
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; NACL-NEXT: .long i
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; NACL-NEXT: .long j
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; MCU-CTORS: .section .ctors,"aw",@progbits
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; MCU-INIT-ARRAY: .section .init_array,"aw",@init_array
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; COFF-CTOR: .section .ctors.65520,"dw",associative,v
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; COFF-CTOR-NEXT: .p2align 3
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; COFF-CTOR-NEXT: .quad g
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; COFF-CTOR-NEXT: .section .ctors.09980,"dw",associative,v
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; COFF-CTOR-NEXT: .p2align 3
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; COFF-CTOR-NEXT: .quad h
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; COFF-CTOR-NEXT: .section .ctors,"dw"
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; COFF-CTOR-NEXT: .p2align 3
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; COFF-CTOR-NEXT: .quad f
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; COFF-CTOR-NEXT: .quad i
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; COFF-CTOR-NEXT: .quad j
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