6ec3e3a728
Inline spiller can decide to move a spill as early as possible in the basic block. It will skip phis and label, but we also need to make sure it skips instructions in the basic block prologue which restore exec mask. Added isPositionLike callback in TargetInstrInfo to detect instructions which shall be skipped in addition to common phis, labels etc. Differential Revision: https://reviews.llvm.org/D27997 llvm-svn: 292554
79 lines
3.2 KiB
LLVM
79 lines
3.2 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs -stress-regalloc=6 < %s | FileCheck %s
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; Inline spiller can decide to move a spill as early as possible in the basic block.
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; It will skip phis and label, but we also need to make sure it skips instructions
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; in the basic block prologue which restore exec mask.
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; Make sure instruction to restore exec mask immediately follows label
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; CHECK-LABEL: {{^}}spill_cfg_position:
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; CHECK: s_cbranch_execz [[LABEL1:BB[0-9_]+]]
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; CHECK: {{^}}[[LABEL1]]:
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; CHECK: s_cbranch_execz [[LABEL2:BB[0-9_]+]]
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; CHECK: {{^}}[[LABEL2]]:
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; CHECK-NEXT: s_or_b64 exec
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; CHECK: buffer_
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define void @spill_cfg_position(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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%tmp14 = load i32, i32 addrspace(1)* %arg, align 4
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%tmp15 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 1
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%tmp16 = load i32, i32 addrspace(1)* %tmp15, align 4
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%tmp17 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 2
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%tmp18 = load i32, i32 addrspace(1)* %tmp17, align 4
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%tmp19 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 3
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%tmp20 = load i32, i32 addrspace(1)* %tmp19, align 4
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%tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 4
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%tmp22 = load i32, i32 addrspace(1)* %tmp21, align 4
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%tmp23 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 5
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%tmp24 = load i32, i32 addrspace(1)* %tmp23, align 4
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%tmp25 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 6
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%tmp26 = load i32, i32 addrspace(1)* %tmp25, align 4
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%tmp27 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 7
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%tmp28 = load i32, i32 addrspace(1)* %tmp27, align 4
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%tmp29 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 8
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%tmp30 = load i32, i32 addrspace(1)* %tmp29, align 4
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%tmp33 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %tmp1
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%tmp34 = load i32, i32 addrspace(1)* %tmp33, align 4
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%tmp35 = icmp eq i32 %tmp34, 0
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br i1 %tmp35, label %bb44, label %bb36
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bb36: ; preds = %bb
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%tmp37 = mul nsw i32 %tmp20, %tmp18
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%tmp38 = add nsw i32 %tmp37, %tmp16
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%tmp39 = mul nsw i32 %tmp24, %tmp22
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%tmp40 = add nsw i32 %tmp38, %tmp39
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%tmp41 = mul nsw i32 %tmp28, %tmp26
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%tmp42 = add nsw i32 %tmp40, %tmp41
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%tmp43 = add nsw i32 %tmp42, %tmp30
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br label %bb52
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bb44: ; preds = %bb
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%tmp45 = mul nsw i32 %tmp18, %tmp16
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%tmp46 = mul nsw i32 %tmp22, %tmp20
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%tmp47 = add nsw i32 %tmp46, %tmp45
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%tmp48 = mul nsw i32 %tmp26, %tmp24
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%tmp49 = add nsw i32 %tmp47, %tmp48
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%tmp50 = mul nsw i32 %tmp30, %tmp28
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%tmp51 = add nsw i32 %tmp49, %tmp50
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br label %bb52
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bb52: ; preds = %bb44, %bb36
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%tmp53 = phi i32 [ %tmp43, %bb36 ], [ %tmp51, %bb44 ]
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%tmp54 = mul nsw i32 %tmp16, %tmp14
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%tmp55 = mul nsw i32 %tmp22, %tmp18
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%tmp56 = mul nsw i32 %tmp24, %tmp20
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%tmp57 = mul nsw i32 %tmp30, %tmp26
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%tmp58 = add i32 %tmp55, %tmp54
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%tmp59 = add i32 %tmp58, %tmp56
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%tmp60 = add i32 %tmp59, %tmp28
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%tmp61 = add i32 %tmp60, %tmp57
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%tmp62 = add i32 %tmp61, %tmp53
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store i32 %tmp62, i32 addrspace(1)* %tmp33, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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