5267edd3e3
Making the cost model selecting between Interleave, GatherScatter or Scalar vectorization form of memory instruction. The right decision should be done for non-consecutive memory access instrcuctions that may have more than one vectorization solution. This patch includes the following changes: - Cost Model calculates the cost of Load/Store vector form and choose the better option between Widening, Interleave, GatherScactter and Scalarization. Cost Model keeps the widening decision. - Arrays of Uniform and Scalar values are moved from Legality to Cost Model. - Cost Model collects Uniforms and Scalars per VF. The collection is based on CM decision map of Loadis/Stores vectorization form. - Vectorization of memory instruction is performed according to the CM decision. Differential Revision: https://reviews.llvm.org/D27919 llvm-svn: 294503
58 lines
2.6 KiB
LLVM
58 lines
2.6 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt < %s -loop-vectorize -instcombine -S -debug-only=loop-vectorize -disable-output -print-after=instcombine 2>&1 | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; CHECK-LABEL: PR31671
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;
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; Check a pointer in which one of its uses is consecutive-like and another of
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; its uses is non-consecutive-like. In the test case below, %tmp3 is the
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; pointer operand of an interleaved load, making it consecutive-like. However,
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; it is also the pointer operand of a non-interleaved store that will become a
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; scatter operation. %tmp3 (and the induction variable) should not be marked
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; uniform-after-vectorization.
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;
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; CHECK: LV: Found uniform instruction: %tmp0 = getelementptr inbounds %data, %data* %d, i64 0, i32 3, i64 %i
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; CHECK-NOT: LV: Found uniform instruction: %tmp3 = getelementptr inbounds %data, %data* %d, i64 0, i32 0, i64 %i
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; CHECK-NOT: LV: Found uniform instruction: %i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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; CHECK-NOT: LV: Found uniform instruction: %i.next = add nuw nsw i64 %i, 5
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; CHECK: vector.body:
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; CHECK: %index = phi i64
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; CHECK: %vec.ind = phi <16 x i64>
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; CHECK: %[[T0:.+]] = mul i64 %index, 5
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; CHECK: %[[T1:.+]] = getelementptr inbounds %data, %data* %d, i64 0, i32 3, i64 %[[T0]]
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; CHECK: %[[T2:.+]] = bitcast float* %[[T1]] to <80 x float>*
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; CHECK: load <80 x float>, <80 x float>* %[[T2]], align 4
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; CHECK: %[[T3:.+]] = getelementptr inbounds %data, %data* %d, i64 0, i32 0, i64 %[[T0]]
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; CHECK: %[[T4:.+]] = bitcast float* %[[T3]] to <80 x float>*
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; CHECK: load <80 x float>, <80 x float>* %[[T4]], align 4
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; CHECK: %VectorGep = getelementptr inbounds %data, %data* %d, i64 0, i32 0, <16 x i64> %vec.ind
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; CHECK: call void @llvm.masked.scatter.v16f32({{.*}}, <16 x float*> %VectorGep, {{.*}})
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; CHECK: br i1 {{.*}}, label %middle.block, label %vector.body
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%data = type { [32000 x float], [3 x i32], [4 x i8], [32000 x float] }
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define void @PR31671(float %x, %data* %d) #0 {
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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%tmp0 = getelementptr inbounds %data, %data* %d, i64 0, i32 3, i64 %i
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%tmp1 = load float, float* %tmp0, align 4
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%tmp2 = fmul float %x, %tmp1
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%tmp3 = getelementptr inbounds %data, %data* %d, i64 0, i32 0, i64 %i
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%tmp4 = load float, float* %tmp3, align 4
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%tmp5 = fadd float %tmp4, %tmp2
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store float %tmp5, float* %tmp3, align 4
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%i.next = add nuw nsw i64 %i, 5
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%cond = icmp slt i64 %i.next, 32000
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br i1 %cond, label %for.body, label %for.end
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for.end:
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ret void
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}
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attributes #0 = { "target-cpu"="knl" }
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