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clang-p2996/llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
Nikita Popov 90ba33099c [InstCombine] Canonicalize constant GEPs to i8 source element type (#68882) 
This patch canonicalizes getelementptr instructions with constant
indices to use the `i8` source element type. This makes it easier for
optimizations to recognize that two GEPs are identical, because they
don't need to see past many different ways to express the same offset.

This is a first step towards
https://discourse.llvm.org/t/rfc-replacing-getelementptr-with-ptradd/68699.
This is limited to constant GEPs only for now, as they have a clear
canonical form, while we're not yet sure how exactly to deal with
variable indices.

The test llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll gives
two representative examples of the kind of optimization improvement we
expect from this change. In the first test SimplifyCFG can now realize
that all switch branches are actually the same. In the second test it
can convert it into simple arithmetic. These are representative of
common optimization failures we see in Rust.

Fixes https://github.com/llvm/llvm-project/issues/69841.
2024-01-24 15:25:29 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -passes='default<O3>' -S | FileCheck %s
; This test after a lot of cleanup should produce pick a tail-predicated 8x
; vector loop. The 8x will be more profitable, to pick a VQDMULH.s16 instruction.
; FIXME: Tailpredicate too, but not at the expense of 8x vectorized.
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
define void @arm_mult_q15(ptr %pSrcA, ptr %pSrcB, ptr noalias %pDst, i32 %blockSize) #0 {
; CHECK-LABEL: @arm_mult_q15(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[CMP_NOT2:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
; CHECK-NEXT: br i1 [[CMP_NOT2]], label [[WHILE_END:%.*]], label [[WHILE_BODY_PREHEADER:%.*]]
; CHECK: while.body.preheader:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[BLOCKSIZE]], 8
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[WHILE_BODY_PREHEADER16:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_VEC:%.*]] = and i32 [[BLOCKSIZE]], -8
; CHECK-NEXT: [[IND_END:%.*]] = and i32 [[BLOCKSIZE]], 7
; CHECK-NEXT: [[TMP0:%.*]] = shl i32 [[N_VEC]], 1
; CHECK-NEXT: [[IND_END7:%.*]] = getelementptr i8, ptr [[PSRCA:%.*]], i32 [[TMP0]]
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[N_VEC]], 1
; CHECK-NEXT: [[IND_END9:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i32 [[TMP1]]
; CHECK-NEXT: [[TMP2:%.*]] = shl i32 [[N_VEC]], 1
; CHECK-NEXT: [[IND_END11:%.*]] = getelementptr i8, ptr [[PSRCB:%.*]], i32 [[TMP2]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[INDEX]], 1
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRCA]], i32 [[TMP3]]
; CHECK-NEXT: [[TMP4:%.*]] = shl i32 [[INDEX]], 1
; CHECK-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[PDST]], i32 [[TMP4]]
; CHECK-NEXT: [[TMP5:%.*]] = shl i32 [[INDEX]], 1
; CHECK-NEXT: [[NEXT_GEP14:%.*]] = getelementptr i8, ptr [[PSRCB]], i32 [[TMP5]]
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[NEXT_GEP]], align 2
; CHECK-NEXT: [[TMP6:%.*]] = sext <8 x i16> [[WIDE_LOAD]] to <8 x i32>
; CHECK-NEXT: [[WIDE_LOAD15:%.*]] = load <8 x i16>, ptr [[NEXT_GEP14]], align 2
; CHECK-NEXT: [[TMP7:%.*]] = sext <8 x i16> [[WIDE_LOAD15]] to <8 x i32>
; CHECK-NEXT: [[TMP8:%.*]] = mul nsw <8 x i32> [[TMP7]], [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = ashr <8 x i32> [[TMP8]], <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
; CHECK-NEXT: [[TMP10:%.*]] = tail call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[TMP9]], <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
; CHECK-NEXT: [[TMP11:%.*]] = trunc <8 x i32> [[TMP10]] to <8 x i16>
; CHECK-NEXT: store <8 x i16> [[TMP11]], ptr [[NEXT_GEP13]], align 2
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N_VEC]], [[BLOCKSIZE]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END]], label [[WHILE_BODY_PREHEADER16]]
; CHECK: while.body.preheader16:
; CHECK-NEXT: [[BLKCNT_06_PH:%.*]] = phi i32 [ [[BLOCKSIZE]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END]], [[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[PSRCA_ADDR_05_PH:%.*]] = phi ptr [ [[PSRCA]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END7]], [[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[PDST_ADDR_04_PH:%.*]] = phi ptr [ [[PDST]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END9]], [[MIDDLE_BLOCK]] ]
; CHECK-NEXT: [[PSRCB_ADDR_03_PH:%.*]] = phi ptr [ [[PSRCB]], [[WHILE_BODY_PREHEADER]] ], [ [[IND_END11]], [[MIDDLE_BLOCK]] ]
; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
; CHECK: while.body:
; CHECK-NEXT: [[BLKCNT_06:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BLKCNT_06_PH]], [[WHILE_BODY_PREHEADER16]] ]
; CHECK-NEXT: [[PSRCA_ADDR_05:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[PSRCA_ADDR_05_PH]], [[WHILE_BODY_PREHEADER16]] ]
; CHECK-NEXT: [[PDST_ADDR_04:%.*]] = phi ptr [ [[INCDEC_PTR4:%.*]], [[WHILE_BODY]] ], [ [[PDST_ADDR_04_PH]], [[WHILE_BODY_PREHEADER16]] ]
; CHECK-NEXT: [[PSRCB_ADDR_03:%.*]] = phi ptr [ [[INCDEC_PTR1:%.*]], [[WHILE_BODY]] ], [ [[PSRCB_ADDR_03_PH]], [[WHILE_BODY_PREHEADER16]] ]
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[PSRCA_ADDR_05]], i32 2
; CHECK-NEXT: [[TMP13:%.*]] = load i16, ptr [[PSRCA_ADDR_05]], align 2
; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP13]] to i32
; CHECK-NEXT: [[INCDEC_PTR1]] = getelementptr inbounds i8, ptr [[PSRCB_ADDR_03]], i32 2
; CHECK-NEXT: [[TMP14:%.*]] = load i16, ptr [[PSRCB_ADDR_03]], align 2
; CHECK-NEXT: [[CONV2:%.*]] = sext i16 [[TMP14]] to i32
; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[CONV2]], [[CONV]]
; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[MUL]], 15
; CHECK-NEXT: [[SPEC_SELECT_I:%.*]] = tail call i32 @llvm.smin.i32(i32 [[SHR]], i32 32767)
; CHECK-NEXT: [[CONV3:%.*]] = trunc i32 [[SPEC_SELECT_I]] to i16
; CHECK-NEXT: [[INCDEC_PTR4]] = getelementptr inbounds i8, ptr [[PDST_ADDR_04]], i32 2
; CHECK-NEXT: store i16 [[CONV3]], ptr [[PDST_ADDR_04]], align 2
; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_06]], -1
; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END]], label [[WHILE_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: while.end:
; CHECK-NEXT: ret void
;
entry:
%pSrcA.addr = alloca ptr, align 4
%pSrcB.addr = alloca ptr, align 4
%pDst.addr = alloca ptr, align 4
%blockSize.addr = alloca i32, align 4
%blkCnt = alloca i32, align 4
store ptr %pSrcA, ptr %pSrcA.addr, align 4
store ptr %pSrcB, ptr %pSrcB.addr, align 4
store ptr %pDst, ptr %pDst.addr, align 4
store i32 %blockSize, ptr %blockSize.addr, align 4
call void @llvm.lifetime.start.p0(i64 4, ptr %blkCnt) #3
%0 = load i32, ptr %blockSize.addr, align 4
store i32 %0, ptr %blkCnt, align 4
br label %while.cond
while.cond: ; preds = %while.body, %entry
%1 = load i32, ptr %blkCnt, align 4
%cmp = icmp ugt i32 %1, 0
br i1 %cmp, label %while.body, label %while.end
while.body: ; preds = %while.cond
%2 = load ptr, ptr %pSrcA.addr, align 4
%incdec.ptr = getelementptr inbounds i16, ptr %2, i32 1
store ptr %incdec.ptr, ptr %pSrcA.addr, align 4
%3 = load i16, ptr %2, align 2
%conv = sext i16 %3 to i32
%4 = load ptr, ptr %pSrcB.addr, align 4
%incdec.ptr1 = getelementptr inbounds i16, ptr %4, i32 1
store ptr %incdec.ptr1, ptr %pSrcB.addr, align 4
%5 = load i16, ptr %4, align 2
%conv2 = sext i16 %5 to i32
%mul = mul nsw i32 %conv, %conv2
%shr = ashr i32 %mul, 15
%call = call i32 @__SSAT(i32 %shr, i32 16)
%conv3 = trunc i32 %call to i16
%6 = load ptr, ptr %pDst.addr, align 4
%incdec.ptr4 = getelementptr inbounds i16, ptr %6, i32 1
store ptr %incdec.ptr4, ptr %pDst.addr, align 4
store i16 %conv3, ptr %6, align 2
%7 = load i32, ptr %blkCnt, align 4
%dec = add i32 %7, -1
store i32 %dec, ptr %blkCnt, align 4
br label %while.cond
while.end: ; preds = %while.cond
call void @llvm.lifetime.end.p0(i64 4, ptr %blkCnt) #3
ret void
}
declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #1
define internal i32 @__SSAT(i32 %val, i32 %sat) #2 {
entry:
%retval = alloca i32, align 4
%val.addr = alloca i32, align 4
%sat.addr = alloca i32, align 4
%max = alloca i32, align 4
%min = alloca i32, align 4
%cleanup.dest.slot = alloca i32, align 4
store i32 %val, ptr %val.addr, align 4
store i32 %sat, ptr %sat.addr, align 4
%0 = load i32, ptr %sat.addr, align 4
%cmp = icmp uge i32 %0, 1
br i1 %cmp, label %land.lhs.true, label %if.end10
land.lhs.true: ; preds = %entry
%1 = load i32, ptr %sat.addr, align 4
%cmp1 = icmp ule i32 %1, 32
br i1 %cmp1, label %if.then, label %if.end10
if.then: ; preds = %land.lhs.true
call void @llvm.lifetime.start.p0(i64 4, ptr %max) #3
%2 = load i32, ptr %sat.addr, align 4
%sub = sub i32 %2, 1
%shl = shl i32 1, %sub
%sub2 = sub i32 %shl, 1
store i32 %sub2, ptr %max, align 4
call void @llvm.lifetime.start.p0(i64 4, ptr %min) #3
%3 = load i32, ptr %max, align 4
%sub3 = sub nsw i32 -1, %3
store i32 %sub3, ptr %min, align 4
%4 = load i32, ptr %val.addr, align 4
%5 = load i32, ptr %max, align 4
%cmp4 = icmp sgt i32 %4, %5
br i1 %cmp4, label %if.then5, label %if.else
if.then5: ; preds = %if.then
%6 = load i32, ptr %max, align 4
store i32 %6, ptr %retval, align 4
store i32 1, ptr %cleanup.dest.slot, align 4
br label %cleanup
if.else: ; preds = %if.then
%7 = load i32, ptr %val.addr, align 4
%8 = load i32, ptr %min, align 4
%cmp6 = icmp slt i32 %7, %8
br i1 %cmp6, label %if.then7, label %if.end
if.then7: ; preds = %if.else
%9 = load i32, ptr %min, align 4
store i32 %9, ptr %retval, align 4
store i32 1, ptr %cleanup.dest.slot, align 4
br label %cleanup
if.end: ; preds = %if.else
br label %if.end8
if.end8: ; preds = %if.end
store i32 0, ptr %cleanup.dest.slot, align 4
br label %cleanup
cleanup: ; preds = %if.end8, %if.then7, %if.then5
call void @llvm.lifetime.end.p0(i64 4, ptr %min) #3
call void @llvm.lifetime.end.p0(i64 4, ptr %max) #3
%cleanup.dest = load i32, ptr %cleanup.dest.slot, align 4
switch i32 %cleanup.dest, label %unreachable [
i32 0, label %cleanup.cont
i32 1, label %return
]
cleanup.cont: ; preds = %cleanup
br label %if.end10
if.end10: ; preds = %cleanup.cont, %land.lhs.true, %entry
%10 = load i32, ptr %val.addr, align 4
store i32 %10, ptr %retval, align 4
br label %return
return: ; preds = %if.end10, %cleanup
%11 = load i32, ptr %retval, align 4
ret i32 %11
unreachable: ; preds = %cleanup
unreachable
}
declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture) #1
attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
attributes #1 = { argmemonly nofree nosync nounwind willreturn }
attributes #2 = { alwaysinline nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
attributes #3 = { nounwind }
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