Eli Friedman 1a78b0bd38 [MachineOutliner] Teach outliner to set live-ins ...

Preserving liveness can be useful even late in the pipeline, if we're
doing substantial optimization work afterwards. (See, for example,
D76065.) Teach MachineOutliner how to correctly set live-ins on the
basic block in outlined functions.

Differential Revision: https://reviews.llvm.org/D78605

2020-04-22 14:19:26 -07:00

..

AsmParser

[RISCV][AsmParser] Implement .option (no)pic

2020-04-17 12:08:30 +00:00

Disassembler

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

MCTargetDesc

[MC][Bugfix] Remove redundant parameter for relaxInstruction

2020-04-21 11:06:55 +08:00

TargetInfo

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Utils

[RISCV] Support ABI checking with per function target-features

2020-01-22 08:12:28 -08:00

CMakeLists.txt

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LLVMBuild.txt

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RISCV.h

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RISCV.td

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

RISCVAsmPrinter.cpp

[RISCV] ELF attribute section for RISC-V.

2020-03-31 16:16:19 +08:00

RISCVCallingConv.td

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RISCVCallLowering.cpp

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RISCVCallLowering.h

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RISCVExpandPseudoInsts.cpp

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RISCVFrameLowering.cpp

CodeGen: Use Register in TargetFrameLowering

2020-04-07 17:07:44 -04:00

RISCVFrameLowering.h

CodeGen: Use Register in TargetFrameLowering

2020-04-07 17:07:44 -04:00

RISCVInstrFormats.td

[RISCV] Scheduler description for the Rocket core

2020-01-23 19:36:47 -06:00

RISCVInstrFormatsC.td

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RISCVInstrInfo.cpp

[MachineOutliner] Teach outliner to set live-ins

2020-04-22 14:19:26 -07:00

RISCVInstrInfo.h

[NFC] unsigned->Register in storeRegTo/loadRegFromStack

2020-02-03 14:22:16 +01:00

RISCVInstrInfo.td

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

RISCVInstrInfoA.td

[RISCV] Scheduler description for the Rocket core

2020-01-23 19:36:47 -06:00

RISCVInstrInfoB.td

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

RISCVInstrInfoC.td

[RISCV] Scheduler description for the Rocket core

2020-01-23 19:36:47 -06:00

RISCVInstrInfoD.td

[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w

2020-03-20 09:42:24 +00:00

RISCVInstrInfoF.td

[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w

2020-03-20 09:42:24 +00:00

RISCVInstrInfoM.td

[RISCV] Scheduler description for the Rocket core

2020-01-23 19:36:47 -06:00

RISCVInstructionSelector.cpp

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RISCVISelDAGToDAG.cpp

[RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp

2020-04-01 11:30:21 +08:00

RISCVISelDAGToDAG.h

[RISCV] Split RISCVISelDAGToDAG.cpp to RISCVISelDAGToDAG.h and RISCVISelDAGToDAG.cpp

2020-04-01 11:30:21 +08:00

RISCVISelLowering.cpp

[CallSite removal][TargetLowering] Replace ImmutableCallSite with CallBase

2020-04-13 13:50:15 -07:00

RISCVISelLowering.h

CodeGen: Use Register in TargetLowering

2020-04-08 12:10:58 -04:00

RISCVLegalizerInfo.cpp

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RISCVLegalizerInfo.h

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RISCVMachineFunctionInfo.h

[RISCV] Add support for save/restore of callee-saved registers via libcalls

2020-02-11 21:23:03 +00:00

RISCVMCInstLower.cpp

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RISCVMergeBaseOffset.cpp

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RISCVRegisterBankInfo.cpp

Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"

2020-03-20 11:02:50 +01:00

RISCVRegisterBankInfo.h

Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"

2020-03-20 11:02:50 +01:00

RISCVRegisterBanks.td

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RISCVRegisterInfo.cpp

CodeGen: More conversions to use Register

2020-04-07 18:54:36 -04:00

RISCVRegisterInfo.h

CodeGen: More conversions to use Register

2020-04-07 18:54:36 -04:00

RISCVRegisterInfo.td

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RISCVSchedRocket32.td

[RISCV] Add new SchedRead SchedWrite

2020-03-10 00:12:27 +08:00

RISCVSchedRocket64.td

[RISCV] Add new SchedRead SchedWrite

2020-03-10 00:12:27 +08:00

RISCVSchedule.td

[RISCV] Add new SchedRead SchedWrite

2020-03-10 00:12:27 +08:00

RISCVSubtarget.cpp

Revert "[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes"

2020-03-20 11:02:50 +01:00

RISCVSubtarget.h

[RISCV] Add MC layer support for proposed Bit Manipulation extension (version 0.92)

2020-04-09 18:04:22 +01:00

RISCVSystemOperands.td

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RISCVTargetMachine.cpp

[RISCV] Check the target-abi module flag matches the option

2020-01-21 07:32:12 -08:00

RISCVTargetMachine.h

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RISCVTargetObjectFile.cpp

[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile

2020-03-20 21:57:34 -07:00

RISCVTargetObjectFile.h

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RISCVTargetTransformInfo.cpp

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RISCVTargetTransformInfo.h

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