071a099102
The two changes together weakened the test and caused a regression with division handling in MSVC mode. They were applied to avoid an assertion being triggered in the block frequency analysis. However, the underlying problem was simply being masked rather than solved properly. Address the actual underlying problem and revert the changes. Rather than analyze the cause of the assertion, the division failure was assumed to be an overflow. The underlying issue was a subtle bug in the BB construction in the emission of the div-by-zero check (WIN__DBZCHK). We did not construct the proper successor information in the basic blocks, nor did we update the PHIs associated with the basic block when we split them. This would result in assertions being triggered in the block frequency analysis pass. Although the original tests are being removed, the tests themselves performed very little in terms of validation but merely tested that we did not assert when generating code. Update this with new tests that actually ensure that we do not regress on the code generation. llvm-svn: 263714
50 lines
1.0 KiB
LLVM
50 lines
1.0 KiB
LLVM
; RUN: llc -mtriple thumbv7-windows-itanium -filetype asm -o - %s | FileCheck %s
|
|
; RUN: llc -mtriple thumbv7-windows-msvc -filetype asm -o - %s | FileCheck %s
|
|
|
|
define arm_aapcs_vfpcc i32 @sdiv32(i32 %divisor, i32 %divident) {
|
|
entry:
|
|
%div = sdiv i32 %divident, %divisor
|
|
ret i32 %div
|
|
}
|
|
|
|
; CHECK-LABEL: sdiv32:
|
|
; CHECK: cbz r0
|
|
; CHECK: bl __rt_sdiv
|
|
; CHECK: udf.w #249
|
|
|
|
define arm_aapcs_vfpcc i32 @udiv32(i32 %divisor, i32 %divident) {
|
|
entry:
|
|
%div = udiv i32 %divident, %divisor
|
|
ret i32 %div
|
|
}
|
|
|
|
; CHECK-LABEL: udiv32:
|
|
; CHECK: cbz r0
|
|
; CHECK: bl __rt_udiv
|
|
; CHECK: udf.w #249
|
|
|
|
define arm_aapcs_vfpcc i64 @sdiv64(i64 %divisor, i64 %divident) {
|
|
entry:
|
|
%div = sdiv i64 %divident, %divisor
|
|
ret i64 %div
|
|
}
|
|
|
|
; CHECK-LABEL: sdiv64:
|
|
; CHECK: orr.w r12, r0, r1
|
|
; CHECK-NEXT: cbz r12
|
|
; CHECK: bl __rt_sdiv64
|
|
; CHECK: udf.w #249
|
|
|
|
define arm_aapcs_vfpcc i64 @udiv64(i64 %divisor, i64 %divident) {
|
|
entry:
|
|
%div = udiv i64 %divident, %divisor
|
|
ret i64 %div
|
|
}
|
|
|
|
; CHECK-LABEL: udiv64:
|
|
; CHECK: orr.w r12, r0, r1
|
|
; CHECK-NEXT: cbz r12
|
|
; CHECK: bl __rt_udiv64
|
|
; CHECK: udf.w #249
|
|
|