Deric Cheung 305d273894 Reland "[HLSL] Implement the reflect HLSL function" (#125599) ...

This PR relands #122992.

A reland was attempted before (#123853), but it [failed to pass the
`sanitizer-aarch64-linux-bootstrap-hwasan`
buildbot](https://github.com/llvm/llvm-project/pull/123853#issuecomment-2608389396)
due to the test `llvm/test/CodeGen/SPIRV/opencl/reflect-error.ll`

The issue has since been patched thanks to @vitalybuka, so the PR is
safe to reland without any changes.
See
https://github.com/llvm/llvm-project/pull/125599#discussion_r1966650839
and
https://github.com/llvm/llvm-project/pull/125599#discussion_r1966650839

2025-02-24 16:46:59 -08:00

..

AArch64

[MachineSched] Add a first valid reason [nfc]

2025-02-24 16:04:30 -08:00

AMDGPU

[AMDGPU] Update PromoteAlloca to handle GEPs with variable offset. (#122342)

2025-02-24 13:36:30 -06:00

ARC

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ARM

[DAG] shouldReduceLoadWidth - hasOneUse should check just the loaded value - not the chain (#128167)

2025-02-24 11:09:41 +00:00

AVR

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BPF

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CSKY

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DirectX

[HLSL] Add more tests to root signature metadata extraction (#127283)

2025-02-18 11:40:29 -08:00

Generic

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Hexagon

[Hexagon] Explicitly truncate constant in UAddSubO (#127360)

2025-02-17 09:30:48 -06:00

Inputs

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Lanai

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LoongArch

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

M68k

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Mips

[Mips] Reserve hardware register HWR2 (#127775)

2025-02-20 20:53:30 +08:00

MIR

[NVPTX] Remove redundant addressing mode instrs (#128044)

2025-02-20 14:51:06 -08:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Support for memory orderings for cmpxchg (#126159)

2025-02-24 10:13:23 -08:00

PowerPC

[NFC] add a pre-commit test case for patch #127121 that hoists xxsplitib out of loop (#127701)

2025-02-21 10:29:52 -05:00

RISCV

[RISCV] Add Qualcomm uC Xqcilia (Large Immediate Arithmetic) extension (#124706)

2025-02-24 08:04:29 -08:00

SPARC

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

SPIRV

Reland "[HLSL] Implement the reflect HLSL function" (#125599)

2025-02-24 16:46:59 -08:00

SystemZ

[SystemZ] Add codegen support for llvm.roundeven

2025-02-14 00:10:37 +01:00

Thumb

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Thumb2

PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)

2025-02-22 09:16:14 +07:00

VE

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

WebAssembly

[WebAssembly] Enable interleaved memory accesses (#125696)

2025-02-17 09:09:52 +00:00

WinCFGuard

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WinEH

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X86

[X86] Fix arithmetic error in extractVector (#128052)

2025-02-24 21:39:28 +08:00

XCore

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Xtensa

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