clang-p2996

AsmParser

[AArch64] Add support for secrel add/load/store relocations for COFF

2018-03-01 20:42:28 +00:00

Disassembler

[AArch64][SVE] Asm: Add AND_ZI instructions and aliases

2018-02-06 13:13:21 +00:00

InstPrinter

[AArch64][AsmParser] NFC: Generalize LogicalImm[Not](32|64) code

2018-01-29 13:05:38 +00:00

MCTargetDesc

Delete code that is probably dead since r249303.

2018-03-08 00:17:13 +00:00

TargetInfo

Add backend name to Target to enable runtime info to be fed back into TableGen

2017-11-15 23:55:44 +00:00

Utils

[AArch64][SVE] Asm: Predicate patterns

2018-01-22 10:46:00 +00:00

AArch64.h

[AArch64] Avoid SIMD interleaved store instruction for Exynos.

2017-12-08 00:58:49 +00:00

AArch64.td

[PATCH] [AArch64] Add new target feature to fuse conditional select

2018-02-23 19:27:43 +00:00

AArch64A53Fix835769.cpp

Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering

2017-11-08 01:01:31 +00:00

AArch64A57FPLoadBalancing.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64AdvSIMDScalarPass.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64AsmPrinter.cpp

[CodeGen] Hoist common AsmPrinter code out of X86, ARM, and AArch64

2018-01-17 23:55:23 +00:00

AArch64CallingConvention.h

Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layering

2017-11-08 01:01:31 +00:00

AArch64CallingConvention.td

[AArch64] Implement dynamic stack probing for windows

2018-02-17 14:26:32 +00:00

AArch64CallLowering.cpp

Fix layering by moving ValueTypes.h from CodeGen to IR

2018-03-23 23:58:31 +00:00

AArch64CallLowering.h

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AArch64CleanupLocalDynamicTLSPass.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64CollectLOH.cpp

Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print"

2018-02-19 15:08:49 +00:00

AArch64CondBrTuning.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64ConditionalCompares.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64ConditionOptimizer.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64DeadRegisterDefinitionsPass.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64ExpandPseudoInsts.cpp

[AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/str

2018-03-12 18:47:43 +00:00

AArch64FalkorHWPFFix.cpp

State that CFG is preserved in 'Falkor HW Prefetch Fix Late Phase'.

2018-03-22 23:44:40 +00:00

AArch64FastISel.cpp

Fix layering by moving ValueTypes.h from CodeGen to IR

2018-03-23 23:58:31 +00:00

AArch64FrameLowering.cpp

[AArch64] Emit CSR loads in the same order as stores

2018-03-14 20:34:03 +00:00

AArch64FrameLowering.h

Move TargetFrameLowering.h to CodeGen where it's implemented

2017-11-03 22:32:11 +00:00

AArch64GenRegisterBankInfo.def

[AArch64][RegisterBankInfo] Teach instruction mapping about gpr32 -> fpr16 cross copies

2017-11-18 04:28:56 +00:00

AArch64InstrAtomics.td

[AArch64] Improve v8.1-A code-gen for atomic load-and

2018-02-12 17:03:11 +00:00

AArch64InstrFormats.td

TableGen: Check the dynamic type of !cast<Rec>(string)

2018-03-19 14:14:20 +00:00

AArch64InstrInfo.cpp

[MachineOutliner] AArch64: Emit CFI instructions when outlining calls

2018-03-19 22:48:40 +00:00

AArch64InstrInfo.h

[AArch64] Refactor stand alone methods (NFC)

2018-02-09 16:14:41 +00:00

AArch64InstrInfo.td

[AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into a following ldr/str

2018-03-12 18:47:43 +00:00

AArch64InstructionSelector.cpp

[AArch64][GlobalISel] When copying from a gpr32 to an fpr16 reg, convert to fpr32 first.

2018-02-20 05:11:57 +00:00

AArch64ISelDAGToDAG.cpp

[AArch64] Fix UB about shift amount exceeds data bit-width

2018-03-08 00:28:25 +00:00

AArch64ISelLowering.cpp

Fix layering by moving ValueTypes.h from CodeGen to IR

2018-03-23 23:58:31 +00:00

AArch64ISelLowering.h

[AArch64] Don't reduce the width of loads if it prevents combining a shift

2018-03-23 14:47:07 +00:00

AArch64LegalizerInfo.cpp

Fix layering by moving ValueTypes.h from CodeGen to IR

2018-03-23 23:58:31 +00:00

AArch64LegalizerInfo.h

[aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal

2017-11-28 20:21:15 +00:00

AArch64LoadStoreOptimizer.cpp

[CodeGen] Add a new pass for PostRA sink

2018-03-22 20:06:47 +00:00

AArch64MachineFunctionInfo.h

…

AArch64MacroFusion.cpp

[PATCH] [AArch64] Add new target feature to fuse conditional select

2018-02-23 19:27:43 +00:00

AArch64MacroFusion.h

…

AArch64MCInstLower.cpp

Move TargetLoweringObjectFile from CodeGen to Target to fix layering

2018-03-23 23:58:19 +00:00

AArch64MCInstLower.h

…

AArch64PBQPRegAlloc.cpp

Rename LiveIntervalAnalysis.h to LiveIntervals.h

2017-12-13 02:51:04 +00:00

AArch64PBQPRegAlloc.h

…

AArch64PerfectShuffle.h

…

AArch64PromoteConstant.cpp

…

AArch64RedundantCopyElimination.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64RegisterBankInfo.cpp

[AArch64] Map G_LOAD on FPR when the definition goes to a copy to FPR

2017-11-18 04:28:59 +00:00

AArch64RegisterBankInfo.h

[AArch64][RegisterBankInfo] Add mapping for G_FPEXT.

2017-11-02 23:38:19 +00:00

AArch64RegisterBanks.td

[aarch64][globalisel] Register banks and classes should have distinct names.

2017-10-18 00:12:43 +00:00

AArch64RegisterInfo.cpp

[AArch64] Implement dynamic stack probing for windows

2018-02-17 14:26:32 +00:00

AArch64RegisterInfo.h

[AArch64] Implement dynamic stack probing for windows

2018-02-17 14:26:32 +00:00

AArch64RegisterInfo.td

[AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors.

2018-01-03 10:15:46 +00:00

AArch64SchedA53.td

[AArch64] Clean-up a few over-eager regexps in models.

2018-03-23 11:00:42 +00:00

AArch64SchedA57.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedA57WriteRes.td

…

AArch64SchedCyclone.td

[AArch64][SVE] Asm: Set SVE as unsupported feature for existing scheduler models.

2017-11-07 15:03:11 +00:00

AArch64SchedExynosM1.td

[AArch64][NFC] Make all ProcResource definitions include their SchedModel.

2018-02-01 12:12:01 +00:00

AArch64SchedExynosM3.td

[AArch64] Adjust the cost model for Exynos M3

2018-03-20 20:00:29 +00:00

AArch64SchedFalkor.td

[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.

2018-03-18 19:56:15 +00:00

AArch64SchedFalkorDetails.td

[AArch64][Falkor] Correct load/store increment scheduling details

2018-03-20 13:46:35 +00:00

AArch64SchedKryo.td

[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.

2018-03-18 19:56:15 +00:00

AArch64SchedKryoDetails.td

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AArch64SchedThunderX2T99.td

[AArch64] Clean-up a few over-eager regexps in models.

2018-03-23 11:00:42 +00:00

AArch64SchedThunderX.td

[TableGen] When trying to reuse a scheduler class for instructions from an InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU.

2018-03-18 19:56:15 +00:00

AArch64Schedule.td

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AArch64SelectionDAGInfo.cpp

AArch64/X86: Factor out common bzero logic; NFC

2017-12-18 23:14:28 +00:00

AArch64SelectionDAGInfo.h

…

AArch64SIMDInstrOpt.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64StorePairSuppress.cpp

MachineFunction: Return reference from getFunction(); NFC

2017-12-15 22:22:58 +00:00

AArch64Subtarget.cpp

[AArch64] Properly handle dllimport of variables when using fast-isel

2018-01-30 19:50:51 +00:00

AArch64Subtarget.h

[PATCH] [AArch64] Add new target feature to fuse conditional select

2018-02-23 19:27:43 +00:00

AArch64SVEInstrInfo.td

[AArch64][SVE] Asm: Add AND_ZI instructions and aliases

2018-02-06 13:13:21 +00:00

AArch64SystemOperands.td

[AArch64] Fix spelling of ICH_ELRSR_EL2 system register

2018-02-06 09:39:04 +00:00

AArch64TargetMachine.cpp

Move TargetLoweringObjectFile from CodeGen to Target to fix layering

2018-03-23 23:58:19 +00:00

AArch64TargetMachine.h

(Re-landing) Expose a TargetMachine::getTargetTransformInfo function

2017-12-22 18:21:59 +00:00

AArch64TargetObjectFile.cpp

…

AArch64TargetObjectFile.h

Move TargetLoweringObjectFile from CodeGen to Target to fix layering

2018-03-23 23:58:19 +00:00

AArch64TargetTransformInfo.cpp

[AArch64] Implement getArithmeticReductionCost

2018-03-16 11:34:15 +00:00

AArch64TargetTransformInfo.h

[AArch64] Implement getArithmeticReductionCost

2018-03-16 11:34:15 +00:00

CMakeLists.txt

[AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features.

2017-12-08 22:04:13 +00:00

LLVMBuild.txt

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SVEInstrFormats.td

[AArch64][SVE] Asm: Add AND_ZI instructions and aliases

2018-02-06 13:13:21 +00:00