caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
351e4fa0e2c98bd24dfd8b547f366e00a4d554b2
clang-p2996/llvm/lib/Target/AMDGPU
History
Mandeep Singh Grang 860adef9e6 [AMDGPU] Change std::sort to llvm::sort in response to r327219 
Summary:
r327219 added wrappers to std::sort which randomly shuffle the container before sorting.
This will help in uncovering non-determinism caused due to undefined sorting
order of objects having the same key.

To make use of that infrastructure we need to invoke llvm::sort instead of std::sort.

Reviewers: tstellar, RKSimon, arsenm

Reviewed By: arsenm

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D44856

llvm-svn: 328429
2018-03-24 17:15:04 +00:00
..
AsmParser
Fix layering of MachineValueType.h by moving it from CodeGen to Support
2018-03-23 23:58:25 +00:00
Disassembler
[AMDGPU][MC] Corrected GATHER4 opcodes
2018-03-12 15:03:34 +00:00
InstPrinter
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
2018-03-16 16:38:04 +00:00
MCTargetDesc
AMDGPU: Remove unused private member of AMDGPUTargetELFStreamer
2018-02-16 23:04:11 +00:00
TargetInfo
Add backend name to Target to enable runtime info to be fed back into TableGen
2017-11-15 23:55:44 +00:00
Utils
[AMDGPU] Add default ISA version targets
2018-03-06 18:33:55 +00:00
AMDGPU.h
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
AMDGPU.td
AMDGPU: Add fast fmaf feature to gfx702
2018-02-27 21:46:15 +00:00
AMDGPUAliasAnalysis.cpp
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
AMDGPUAliasAnalysis.h
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
AMDGPUAlwaysInlinePass.cpp
AMDGPU: Add option to stress calls
2017-09-21 07:00:48 +00:00
AMDGPUAnnotateKernelFeatures.cpp
[Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes. Also affected in files (NFC).
2017-08-31 21:56:16 +00:00
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUArgumentUsageInfo.cpp
[CodeGen] Rename functions PrintReg* to printReg*
2017-11-28 12:42:37 +00:00
AMDGPUArgumentUsageInfo.h
[AMDGPU] Fixed MSVC build break
2017-08-04 10:53:07 +00:00
AMDGPUAsmPrinter.cpp
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
2018-03-23 23:58:19 +00:00
AMDGPUAsmPrinter.h
[AMDGPU] add labels to +DumpCode output
2017-12-08 14:09:34 +00:00
AMDGPUCallingConv.td
AMDGPU: Initial implementation of calls
2017-08-01 19:54:18 +00:00
AMDGPUCallLowering.cpp
[AMDGPU] Change constant addr space to 4
2018-02-13 18:00:25 +00:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
Reapply "AMDGPU: Add 32-bit constant address space"
2018-02-09 16:57:57 +00:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
Move TargetFrameLowering.h to CodeGen where it's implemented
2017-11-03 22:32:11 +00:00
AMDGPUGenRegisterBankInfo.def
AMDGPU/GlobalISel: Use a more correct getValueMapping
2018-03-01 21:08:51 +00:00
AMDGPUInline.cpp
[AMDGPU] Port of HSAIL inliner
2017-09-20 04:25:58 +00:00
AMDGPUInstrInfo.cpp
Reapply "AMDGPU: Add 32-bit constant address space"
2018-02-09 16:57:57 +00:00
AMDGPUInstrInfo.h
AMDGPU: Fix layering issue
2018-02-09 16:57:48 +00:00
AMDGPUInstrInfo.td
AMDGPU: Add intrinsics llvm.amdgcn.cvt.{pknorm.i16, pknorm.u16, pk.i16, pk.u16}
2018-01-31 20:18:04 +00:00
AMDGPUInstructions.td
[AMDGPU] Supported ds_write_b128 generation.
2018-03-16 18:12:00 +00:00
AMDGPUInstructionSelector.cpp
Reapply "AMDGPU: Add 32-bit constant address space"
2018-02-09 16:57:57 +00:00
AMDGPUInstructionSelector.h
[globalisel][tablegen] Generate rule coverage and use it to identify untested rules
2017-11-16 00:46:35 +00:00
AMDGPUIntrinsicInfo.cpp
…
AMDGPUIntrinsicInfo.h
…
AMDGPUIntrinsics.td
…
AMDGPUISelDAGToDAG.cpp
Fix layering by moving ValueTypes.h from CodeGen to IR
2018-03-23 23:58:31 +00:00
AMDGPUISelLowering.cpp
Pass Divergence Analysis data to Selection DAG to drive divergence
2018-03-05 15:12:21 +00:00
AMDGPUISelLowering.h
AMDGPU: Fix build warning about override
2018-03-05 16:25:10 +00:00
AMDGPULegalizerInfo.cpp
Fix layering by moving ValueTypes.h from CodeGen to IR
2018-03-23 23:58:31 +00:00
AMDGPULegalizerInfo.h
AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
2018-03-08 16:24:16 +00:00
AMDGPULibCalls.cpp
Make helpers static. NFC.
2017-11-24 14:55:41 +00:00
AMDGPULibFunc.cpp
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
2017-11-04 17:37:43 +00:00
AMDGPULibFunc.h
[AMDGPU] Remove hardcoded address space value from AMDGPULibFunc
2017-11-04 17:37:43 +00:00
AMDGPULowerIntrinsics.cpp
…
AMDGPUMachineCFGStructurizer.cpp
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
AMDGPUMachineFunction.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUMachineFunction.h
…
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
AMDGPU: Handle more than one memory operand in SIMemoryLegalizer
2017-09-07 16:14:21 +00:00
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
AMDGPUMCInstLower.h
…
AMDGPUOpenCLEnqueuedBlockLowering.cpp
[AMDGPU] Fix lowering enqueue kernel when kernel has no name
2018-03-12 16:34:06 +00:00
AMDGPUOpenCLImageTypeLoweringPass.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
AMDGPUPromoteAlloca.cpp
AMDGPU/SI: Extend promoting alloca to vector to arrays of up to 16 elements
2018-02-16 19:14:17 +00:00
AMDGPUPTNote.h
AMDGPU/NFC: Move AMDGPU specific note types to ELF.h
2017-10-12 18:59:54 +00:00
AMDGPURegAsmNames.inc.cpp
…
AMDGPURegisterBankInfo.cpp
AMDGPU/GlobalISel: RegBankSelect for basic int ops
2018-03-19 14:07:23 +00:00
AMDGPURegisterBankInfo.h
AMDGPU/GlobalISel: Define instruction mapping for G_OR
2018-03-01 21:25:25 +00:00
AMDGPURegisterBanks.td
AMDGPU/GlobalISel: Define InstrMappings for G_ICMP
2018-03-01 19:27:10 +00:00
AMDGPURegisterInfo.cpp
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
2018-01-24 18:09:53 +00:00
AMDGPURegisterInfo.h
[AMDGPU] Return true in enableMultipleCopyHints().
2018-02-17 10:00:28 +00:00
AMDGPURegisterInfo.td
…
AMDGPURewriteOutArguments.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
AMDGPUSubtarget.cpp
AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo
2018-03-08 16:24:16 +00:00
AMDGPUSubtarget.h
[AMDGPU] Remove use of OpenCL triple environment and replace with function attribute for AMDGPU
2018-03-23 18:45:18 +00:00
AMDGPUTargetMachine.cpp
Move TargetLoweringObjectFile from CodeGen to Target to fix layering
2018-03-23 23:58:19 +00:00
AMDGPUTargetMachine.h
(Re-landing) Expose a TargetMachine::getTargetTransformInfo function
2017-12-22 18:21:59 +00:00
AMDGPUTargetObjectFile.cpp
AMDGPU: Fix set but not used warnings related to AMDGPUAS
2017-11-01 19:12:38 +00:00
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
Fix layering by moving ValueTypes.h from CodeGen to IR
2018-03-23 23:58:31 +00:00
AMDGPUTargetTransformInfo.h
[AMDGPU] Increased vector length for global/constant loads.
2018-03-07 17:09:18 +00:00
AMDGPUUnifyDivergentExitNodes.cpp
Fix a couple of layering violations in Transforms
2018-03-21 22:34:23 +00:00
AMDGPUUnifyMetadata.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-10 00:46:15 +00:00
AMDILCFGStructurizer.cpp
Fix layering of MachineValueType.h by moving it from CodeGen to Support
2018-03-23 23:58:25 +00:00
AMDKernelCodeT.h
[AMDGPU] Revert r310429 changes in AMDKernelCodeT.h which broke some build bots.
2017-08-09 00:06:29 +00:00
BUFInstructions.td
[AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction
2018-03-12 17:29:24 +00:00
CaymanInstructions.td
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
2017-12-07 10:40:31 +00:00
CMakeLists.txt
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
DSInstructions.td
[AMDGPU] Supported ds_write_b128 generation.
2018-03-16 18:12:00 +00:00
EvergreenInstructions.td
AMDGPU: Select BFI patterns with 64-bit ints
2018-02-07 00:21:34 +00:00
FLATInstructions.td
[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes
2017-11-27 17:14:35 +00:00
GCNHazardRecognizer.cpp
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
2017-12-07 20:34:25 +00:00
GCNHazardRecognizer.h
[AMDGPU] Add GCNHazardRecognizer::checkInlineAsmHazards() and GCNHazardRecognizer::checkVALUHazardsHelper(). checkInlineAsmHazards() checks INLINEASM for hazards that we particularly care about (so not exhaustive); this patch adds a check for INLINEASM that defs vregs that hold data-to-be stored by immediately preceding store of more than 8 bytes. If the instr were not within an INLINEASM, this scenario would be handled by checkVALUHazard(). Add checkVALUHazardsHelper(), which will be called by both checkVALUHazards() and checkInlineAsmHazards().
2017-12-07 20:34:25 +00:00
GCNILPSched.cpp
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
GCNIterativeScheduler.cpp
[AMDGPU] Change std::sort to llvm::sort in response to r327219
2018-03-24 17:15:04 +00:00
GCNIterativeScheduler.h
AMDGPU: Partial ILP scheduler port from SelectionDAG to SchedulingDAG (experimental)
2017-11-20 14:35:53 +00:00
GCNMinRegStrategy.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-08 23:53:55 +00:00
GCNProcessors.td
AMDGPU: Bring processors and features in sync with the spec
2018-02-16 21:26:25 +00:00
GCNRegPressure.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
GCNRegPressure.h
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
GCNSchedStrategy.cpp
[NFC] fix trivial typos in comments
2018-01-22 05:54:46 +00:00
GCNSchedStrategy.h
…
LLVMBuild.txt
…
MIMGInstructions.td
[AMDGPU][MC] Corrected GATHER4 opcodes
2018-03-12 15:03:34 +00:00
R600ClauseMergePass.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
R600ControlFlowFinalizer.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
…
R600ExpandSpecialInstrs.cpp
[AMDGPU] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
2017-08-10 00:46:15 +00:00
R600FrameLowering.cpp
…
R600FrameLowering.h
AMDGPU: Initial implementation of calls
2017-08-01 19:54:18 +00:00
R600InstrFormats.td
AMDGPU: Remove global isGCN predicates
2017-10-03 00:06:41 +00:00
R600InstrInfo.cpp
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
2018-01-24 18:09:53 +00:00
R600InstrInfo.h
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
2018-01-24 18:09:53 +00:00
R600Instructions.td
AMDGPU: Move ADDRIndirect complex pattern into R600Instructions.td
2018-01-29 23:29:26 +00:00
R600Intrinsics.td
…
R600ISelLowering.cpp
Fix layering of MachineValueType.h by moving it from CodeGen to Support
2018-03-23 23:58:25 +00:00
R600ISelLowering.h
…
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600OptimizeVectorRegisters.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
R600Packetizer.cpp
AMDGPU/R600: Initialize more passes
2017-08-02 22:19:45 +00:00
R600Processors.td
AMDGPU/EG: Add a new FeatureFMA and use it to selectively enable FMA instruction
2017-12-04 23:07:28 +00:00
R600RegisterInfo.cpp
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
2018-01-24 18:09:53 +00:00
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R700Instructions.td
…
SIAnnotateControlFlow.cpp
Fix a couple of layering violations in Transforms
2018-03-21 22:34:23 +00:00
SIDebuggerInsertNops.cpp
…
SIDefines.h
AMDGPU/SI: Add d16 support for image intrinsics.
2018-01-18 22:08:53 +00:00
SIFixSGPRCopies.cpp
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
SIFixVGPRCopies.cpp
…
SIFixWWMLiveness.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SIFoldOperands.cpp
AMDGPU: Fix crash when constant folding with physreg operand
2018-03-10 16:05:35 +00:00
SIFrameLowering.cpp
[AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shader
2018-02-26 14:46:43 +00:00
SIFrameLowering.h
[AMDGPU] AMDPAL scratch buffer support
2017-09-29 09:49:35 +00:00
SIInsertSkips.cpp
Fix compiler warning introduced in r325931. NFC.
2018-02-23 19:11:33 +00:00
SIInsertWaitcnts.cpp
[AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate info in the case of a single basic block loop. mergeInputScoreBrackets() does this for us; update it so that it processes the single bb's score bracket when processing the single bb's preds. It is, after all, a pred of itself, so it's score bracket is needed.
2018-03-14 22:04:32 +00:00
SIInsertWaits.cpp
[NFC] fix trivial typos in comments
2018-02-22 07:48:29 +00:00
SIInstrFormats.td
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
2018-02-23 18:25:08 +00:00
SIInstrInfo.cpp
Fix layering of MachineValueType.h by moving it from CodeGen to Support
2018-03-23 23:58:25 +00:00
SIInstrInfo.h
[AMDGPU][MC] Added lds support for MUBUF instructions
2018-02-21 13:13:48 +00:00
SIInstrInfo.td
[AMDGPU] Supported ds_write_b128 generation.
2018-03-16 18:12:00 +00:00
SIInstructions.td
[AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes
2018-03-16 16:38:04 +00:00
SIIntrinsics.td
…
SIISelLowering.cpp
Fix layering by moving ValueTypes.h from CodeGen to IR
2018-03-23 23:58:31 +00:00
SIISelLowering.h
AMDGPU/SI: Add d16 support for buffer intrinsics.
2018-01-12 21:12:19 +00:00
SILoadStoreOptimizer.cpp
AMDGPU: Track physreg uses in SILoadStoreOptimizer
2018-02-23 10:45:56 +00:00
SILowerControlFlow.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SILowerI1Copies.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SIMachineFunctionInfo.cpp
Reapply "AMDGPU: Add 32-bit constant address space"
2018-02-09 16:57:57 +00:00
SIMachineFunctionInfo.h
[AMDGPU] stop buffer_store being moved illegally
2018-02-20 10:03:38 +00:00
SIMachineScheduler.cpp
Rename LiveIntervalAnalysis.h to LiveIntervals.h
2017-12-13 02:51:04 +00:00
SIMachineScheduler.h
…
SIMemoryLegalizer.cpp
[AMDGPU] More descriptive names in the memory legalizer
2018-02-09 06:05:33 +00:00
SIOptimizeExecMasking.cpp
[MachineOperand][Target] MachineOperand::isRenamable semantics changes
2018-02-23 18:25:08 +00:00
SIOptimizeExecMaskingPreRA.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SIPeepholeSDWA.cpp
Test commit - change comment slightly.
2018-03-11 03:27:50 +00:00
SIRegisterInfo.cpp
[AMDGPU] : fix for the crash in SIRegisterInfo when the regiser class not found
2018-03-01 17:36:43 +00:00
SIRegisterInfo.h
[AMDGPU] Make sure all super regs of reserved regs are marked reserved.
2018-01-24 18:09:53 +00:00
SIRegisterInfo.td
[AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support
2018-01-10 14:22:19 +00:00
SISchedule.td
…
SIShrinkInstructions.cpp
[AMDGPU] Shrinking V_SUBBREV_U32
2018-02-24 01:32:32 +00:00
SIWholeQuadMode.cpp
MachineFunction: Return reference from getFunction(); NFC
2017-12-15 22:22:58 +00:00
SMInstructions.td
TableGen: Check the dynamic type of !cast<Rec>(string)
2018-03-19 14:14:20 +00:00
SOPInstructions.td
AMDGPU: Add llvm.amdgcn.wqm.vote intrinsic
2017-10-24 10:26:59 +00:00
VIInstrFormats.td
…
VIInstructions.td
…
VOP1Instructions.td
[AMDGPU] Copy impdefs from pseudo to real instructions
2018-01-15 17:55:35 +00:00
VOP2Instructions.td
[AMDGPU] added writelane intrinsic
2018-02-28 19:10:32 +00:00
VOP3Instructions.td
[AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9
2018-03-09 07:21:43 +00:00
VOP3PInstructions.td
AMDGPU: Add max-mix-insts subtarget feature
2017-10-25 07:00:51 +00:00
VOPCInstructions.td
[AMDGPU][MC] Corrected default values for unused SDWA operands
2018-03-16 15:40:27 +00:00
VOPInstructions.td
[AMDGPU][MC] Corrected default values for unused SDWA operands
2018-03-16 15:40:27 +00:00