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clang-p2996/llvm/test/CodeGen/NVPTX
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Artem Belevich 30512869ff [NVPTX] Make tensor shape part of WMMA intrinsic's name. 
This is needed for the upcoming implementation of the
new 8x32x16 and 32x8x16 variants of WMMA instructions
introduced in CUDA 9.1.

Differential Revision: https://reviews.llvm.org/D44719

llvm-svn: 328158
2018-03-21 21:55:02 +00:00
..
access-non-generic.ll
[NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM.
2018-02-28 23:57:48 +00:00
add-128bit.ll
[DAGCombiner] add missing folds for scalar select of {-1,0,1}
2017-02-24 17:17:33 +00:00
addrspacecast-gvar.ll
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addrspacecast.ll
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aggr-param.ll
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aggregate-return.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
alias.ll
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annotations.ll
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arg-lowering.ll
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arithmetic-fp-sm20.ll
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arithmetic-int.ll
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atomics-sm60.ll
[NVPTX] Implement __nvvm_atom_add_gen_d builtin.
2017-11-07 22:10:54 +00:00
atomics-with-scope.ll
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atomics.ll
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barrier.ll
[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
2017-09-21 18:44:49 +00:00
bfe.ll
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branch-fold.ll
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bug17709.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
bug21465.ll
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bug22246.ll
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bug22322.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
bug26185-2.ll
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bug26185.ll
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bypass-div.ll
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call-with-alloca-buffer.ll
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callchain.ll
…
calling-conv.ll
…
combine-min-max.ll
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compare-int.ll
…
constant-vectors.ll
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convergent-mir-call.ll
…
convert-fp.ll
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convert-int-sm20.ll
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ctlz.ll
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
2017-05-12 19:56:43 +00:00
ctpop.ll
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
2017-05-12 19:56:43 +00:00
cttz.ll
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)
2017-05-12 19:56:43 +00:00
disable-opt.ll
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div-ri.ll
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divrem-combine.ll
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envreg.ll
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extloadv.ll
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f16-instructions.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
f16x2-instructions.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
fast-math.ll
[NVPTX] Enable combineRepeatedFPDivisors for NVPTX.
2017-02-03 15:13:50 +00:00
fcos-no-fast-math.ll
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fma-assoc.ll
[DAGCombine] require UnsafeFPMath for re-association of addition
2017-01-31 14:35:37 +00:00
fma-disable.ll
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fma.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
fns.ll
[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.
2017-12-06 17:50:05 +00:00
fp16.ll
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fp-contract.ll
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fp-literals.ll
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fsin-no-fast-math.ll
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function-align.ll
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generic-to-nvvm-ir.ll
[NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM.
2018-02-28 23:57:48 +00:00
generic-to-nvvm.ll
[NVPTX] Use addrspacecast instead of target-specific intrinsics in NVPTXGenericToNVVM.
2018-02-28 23:57:48 +00:00
global-addrspace.ll
…
global-ctor-empty.ll
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global-ctor.ll
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global-dtor.ll
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global-ordering.ll
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global-variable-big.ll
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global-visibility.ll
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globals_init.ll
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globals_lowering.ll
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gvar-init.ll
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half.ll
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i1-global.ll
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i1-int-to-fp.ll
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i1-param.ll
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i8-param.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
i128-global.ll
[NVPTX] Add lowering of i128 params.
2017-07-20 21:16:03 +00:00
i128-param.ll
[NVPTX] Add lowering of i128 params.
2017-07-20 21:16:03 +00:00
i128-retval.ll
[NVPTX] Add lowering of i128 params.
2017-07-20 21:16:03 +00:00
idioms.ll
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imad.ll
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implicit-def.ll
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inline-asm.ll
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intrin-nocapture.ll
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intrinsic-old.ll
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intrinsics.ll
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isspacep.ll
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ld-addrspace.ll
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ld-generic.ll
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ld-st-addrrspace.py
[NVPTX] allow address space inference for volatile loads/stores.
2017-10-24 20:31:44 +00:00
ldg-invariant.ll
[NVPTX] Add tests that invariant vector loads get lowered to ld.global.nc.
2017-02-04 01:54:56 +00:00
ldparam-v4.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
ldu-i8.ll
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ldu-ldg.ll
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ldu-reg-plus-offset.ll
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lit.local.cfg
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load-sext-i1.ll
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load-with-non-coherent-cache.ll
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LoadStoreVectorizer.ll
[NVPTX] Added support for .f16x2 instructions.
2017-02-23 22:38:24 +00:00
local-stack-frame.ll
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loop-vectorize.ll
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lower-aggr-copies.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
lower-alloca.ll
NVPTX: Move InferAddressSpaces to generic code
2017-01-31 01:10:58 +00:00
lower-kernel-ptr-arg.ll
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machine-sink.ll
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MachineSink-call.ll
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MachineSink-convergent.ll
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managed.ll
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match.ll
[NVPTX] added match.{any,all}.sync instructions, intrinsics & builtins.
2017-09-26 17:07:23 +00:00
math-intrins.ll
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minmax-negative.ll
Improve clamp recognition in ValueTracking.
2017-10-27 20:53:41 +00:00
misaligned-vector-ldst.ll
[NVPTX] Fixed lowering of unaligned loads/stores of f16 scalars and vectors.
2017-03-07 20:33:38 +00:00
module-inline-asm.ll
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mulwide.ll
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named-barriers.ll
[NVPTX] Add intrinsics to support named barriers.
2017-01-28 16:38:15 +00:00
noduplicate-syncthreads.ll
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nounroll.ll
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nvcl-param-align.ll
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nvvm-reflect-module-flag.ll
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nvvm-reflect.ll
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param-align.ll
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param-load-store.ll
[DAGCombiner] When combining zero_extend of a truncate, only mask before extending for vectors.
2018-03-01 22:32:25 +00:00
pr13291-i1-store.ll
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pr16278.ll
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pr17529.ll
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read-global-variable-constant.ll
[NVPTX] Lower loads from global constants using ld.global.nc (aka LDG).
2018-02-28 23:58:05 +00:00
refl1.ll
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reg-copy.ll
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reg-types.ll
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rotate.ll
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sched1.ll
Only enable LiveRangeShrink for x86.
2017-05-17 20:18:13 +00:00
sched2.ll
Only enable LiveRangeShrink for x86.
2017-05-17 20:18:13 +00:00
sext-in-reg.ll
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sext-params.ll
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shfl-sync.ll
[NVPTX] Implemented shfl.sync instruction and supporting intrinsics/builtins.
2017-09-20 21:23:07 +00:00
shfl.ll
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shift-parts.ll
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simple-call.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
sm-version-20.ll
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sm-version-21.ll
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sm-version-30.ll
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sm-version-32.ll
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sm-version-35.ll
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sm-version-37.ll
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sm-version-50.ll
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sm-version-52.ll
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sm-version-53.ll
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sm-version-60.ll
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sm-version-61.ll
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sm-version-62.ll
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sm-version-70.ll
[CUDA] Added rudimentary support for CUDA-9 and sm_70.
2017-09-07 18:14:32 +00:00
speculative-execution-divergent-target.ll
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sqrt-approx.ll
[NVPTX] Compute approx sqrt as 1/rsqrt(x) rather than x*rsqrt(x).
2017-01-31 23:08:57 +00:00
st-addrspace.ll
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st-generic.ll
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surf-read-cuda.ll
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surf-read.ll
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surf-write-cuda.ll
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surf-write.ll
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symbol-naming.ll
[NVPTX] Assign valid global names
2017-12-04 14:19:33 +00:00
TailDuplication-convergent.ll
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tex-read-cuda.ll
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tex-read.ll
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texsurf-queries.ll
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tid-range.ll
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tuple-literal.ll
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vec8.ll
Revert r302938 "Add LiveRangeShrink pass to shrink live range within BB."
2017-05-18 18:50:05 +00:00
vec-param-load.ll
[NVPTX] Unify vectorization of load/stores of aggregate arguments and return values.
2017-02-21 22:56:05 +00:00
vector-args.ll
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vector-call.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00
vector-compare.ll
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vector-global.ll
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vector-loads.ll
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vector-select.ll
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vector-stores.ll
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vote.ll
[NVPTX] Implemented bar.warp.sync, barrier.sync, and vote{.sync} instructions/intrinsics/builtins.
2017-09-21 18:44:49 +00:00
weak-global.ll
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weak-linkage.ll
…
wmma.py
[NVPTX] Make tensor shape part of WMMA intrinsic's name.
2018-03-21 21:55:02 +00:00
zero-cs.ll
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zeroext-32bit.ll
[NVPTX] Don't flag StoreParam/LoadParam memory chain operands as ReadMem/WriteMem (PR32146)
2017-05-15 17:17:44 +00:00