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Nemanja Ivanovic 3c7e276d24 [PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16 
As outlined in the PR, we didn't ensure that displacements for DQ-Form
instructions are multiples of 16. Since the instruction encoding encodes
a quad-word displacement, a sub-16 byte displacement is meaningless and
ends up being encoded incorrectly.

Fixes https://bugs.llvm.org/show_bug.cgi?id=33671.

Differential Revision: https://reviews.llvm.org/D35007

llvm-svn: 307934
2017-07-13 18:17:10 +00:00
..
2004-11-29-ShrCrash.ll
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2004-11-30-shift-crash.ll
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2004-11-30-shr-var-crash.ll
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2004-12-12-ZeroSizeCommon.ll
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2005-01-14-SetSelectCrash.ll
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2005-01-14-UndefLong.ll
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2005-08-12-rlwimi-crash.ll
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2005-09-02-LegalizeDuplicatesCalls.ll
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2005-10-08-ArithmeticRotate.ll
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2005-11-30-vastart-crash.ll
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2006-01-11-darwin-fp-argument.ll
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2006-01-20-ShiftPartsCrash.ll
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2006-04-01-FloatDoubleExtend.ll
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2006-04-05-splat-ish.ll
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2006-04-19-vmaddfp-crash.ll
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2006-05-12-rlwimi-crash.ll
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2006-07-07-ComputeMaskedBits.ll
Do full codegen for various tests. NFC
2017-02-27 01:15:57 +00:00
2006-07-19-stwbrx-crash.ll
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2006-08-11-RetVector.ll
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2006-08-15-SelectionCrash.ll
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2006-09-28-shift_64.ll
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2006-10-13-Miscompile.ll
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2006-10-17-brcc-miscompile.ll
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2006-10-17-ppc64-alloca.ll
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2006-11-10-DAGCombineMiscompile.ll
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2006-11-29-AltivecFPSplat.ll
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2006-12-07-LargeAlloca.ll
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2006-12-07-SelectCrash.ll
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2007-01-04-ArgExtension.ll
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2007-01-15-AsmDialect.ll
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2007-01-29-lbrx-asm.ll
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2007-01-31-InlineAsmAddrMode.ll
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2007-02-16-AlignPacked.ll
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2007-02-16-InlineAsmNConstraint.ll
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2007-02-23-lr-saved-twice.ll
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2007-03-24-cntlzd.ll
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2007-03-30-SpillerCrash.ll
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2007-04-24-InlineAsm-I-Modifier.ll
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2007-04-30-InlineAsmEarlyClobber.ll
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2007-05-03-InlineAsm-S-Constraint.ll
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2007-05-14-InlineAsmSelectCrash.ll
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2007-05-22-tailmerge-3.ll
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2007-05-30-dagcombine-miscomp.ll
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2007-06-28-BCCISelBug.ll
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2007-08-04-CoalescerAssert.ll
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2007-09-04-AltivecDST.ll
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2007-09-07-LoadStoreIdxForms.ll
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2007-09-08-unaligned.ll
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2007-09-11-RegCoalescerAssert.ll
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2007-09-12-LiveIntervalsAssert.ll
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2007-10-16-InlineAsmFrameOffset.ll
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2007-10-18-PtrArithmetic.ll
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2007-10-21-LocalRegAllocAssert2.ll
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2007-10-21-LocalRegAllocAssert.ll
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2007-11-04-CoalescerCrash.ll
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2007-11-16-landingpad-split.ll
Turn on -addr-sink-using-gep by default.
2017-04-06 22:42:18 +00:00
2007-11-19-VectorSplitting.ll
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2008-02-05-LiveIntervalsAssert.ll
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2008-02-09-LocalRegAllocAssert.ll
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2008-03-05-RegScavengerAssert.ll
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2008-03-17-RegScavengerCrash.ll
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2008-03-18-RegScavengerAssert.ll
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2008-03-24-AddressRegImm.ll
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2008-03-24-CoalescerBug.ll
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2008-03-26-CoalescerBug.ll
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2008-04-10-LiveIntervalCrash.ll
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2008-04-16-CoalescerBug.ll
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2008-04-23-CoalescerCrash.ll
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2008-05-01-ppc_fp128.ll
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2008-06-19-LegalizerCrash.ll
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2008-06-21-F128LoadStore.ll
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2008-06-23-LiveVariablesCrash.ll
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2008-07-10-SplatMiscompile.ll
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2008-07-15-Bswap.ll
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2008-07-15-Fabs.ll
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2008-07-15-SignExtendInreg.ll
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2008-07-17-Fneg.ll
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2008-07-24-PPC64-CCBug.ll
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2008-09-12-CoalescerBug.ll
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2008-10-17-AsmMatchingOperands.ll
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2008-10-28-f128-i32.ll
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2008-10-28-UnprocessedNode.ll
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2008-10-31-PPCF128Libcalls.ll
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2008-12-02-LegalizeTypeAssert.ll
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2009-01-16-DeclareISelBug.ll
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2009-03-17-LSRBug.ll
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2009-05-28-LegalizeBRCC.ll
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2009-07-16-InlineAsm-M-Operand.ll
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2009-08-17-inline-asm-addr-mode-breakage.ll
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2009-09-18-carrybit.ll
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2009-11-15-ProcImpDefsBug.ll
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2009-11-25-ImpDefBug.ll
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2010-02-04-EmptyGlobal.ll
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2010-02-12-saveCR.ll
RegisterScavenging: Followup to r305625
2017-06-20 18:43:14 +00:00
2010-03-09-indirect-call.ll
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2010-04-01-MachineCSEBug.ll
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2010-05-03-retaddr1.ll
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2010-10-11-Fast-Varargs.ll
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2010-12-18-PPCStackRefs.ll
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2011-12-05-NoSpillDupCR.ll
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2011-12-06-SpillAndRestoreCR.ll
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2011-12-08-DemandedBitsMiscompile.ll
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2012-09-16-TOC-entry-check.ll
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2012-10-11-dynalloc.ll
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2012-10-12-bitcast.ll
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2012-11-16-mischedcall.ll
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2013-05-15-preinc-fold.ll
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2013-07-01-PHIElimBug.ll
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2016-01-07-BranchWeightCrash.ll
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2016-04-16-ADD8TLS.ll
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2016-04-17-combine.ll
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2016-04-28-setjmp.ll
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a2-fp-basic.ll
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a2q-stackalign.ll
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a2q.ll
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aa-tbaa.ll
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aantidep-def-ec.mir
CalleeSavedRegister was removed from MIR and is recalculated upon MIR parsing.
2017-03-19 11:18:09 +00:00
aantidep-inline-asm-use.ll
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add-fi.ll
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addc.ll
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addegluecrash.ll
Fix typo in test filename. NFC
2017-02-11 17:48:49 +00:00
addi-licm.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
addi-offset-fold.ll
[PowerPC] Fix address-offset folding for plain addi
2016-09-07 07:36:11 +00:00
addi-reassoc.ll
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addisdtprelha-nonr3.mir
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
2016-08-25 01:27:13 +00:00
addrfuncstr.ll
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aggressive-anti-dep-breaker-subreg.ll
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alias.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
align.ll
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allocate-r0.ll
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altivec-ord.ll
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and_add.ll
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and_sext.ll
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and_sra.ll
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and-branch.ll
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and-elim.ll
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and-imm.ll
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andc.ll
[DAG] add splat vector support for 'xor' in SimplifyDemandedBits
2017-04-19 21:23:09 +00:00
anon_aggr.ll
[PowerPC] fix incorrect processor name for -mcpu in a test case
2017-06-27 08:35:35 +00:00
anyext_srl.ll
[PPC] Better codegen for AND, ANY_EXT, SRL sequence
2016-10-24 15:46:58 +00:00
arr-fp-arg-no-copy.ll
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ashr-neg1.ll
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asm-constraints.ll
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asm-dialect.ll
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asm-printer-topological-order.ll
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asm-Zy.ll
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asym-regclass-copy.ll
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atomic-1.ll
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atomic-2.ll
[PowerPC] fix potential verification errors on CFENCE8
2017-06-15 16:51:28 +00:00
atomic-minmax.ll
[PowerPC] Implement lowering for atomicrmw min/max/umin/umax
2016-08-28 16:17:58 +00:00
Atomics-64.ll
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atomics-constant.ll
[PowerPC] fix potential verification errors on CFENCE8
2017-06-15 16:51:28 +00:00
atomics-fences.ll
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atomics-indexed.ll
[PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.
2017-05-16 20:18:06 +00:00
atomics-regression.ll
Enhance synchscope representation
2017-07-11 22:23:00 +00:00
atomics.ll
[PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.
2017-05-16 20:18:06 +00:00
available-externally.ll
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bdzlr.ll
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big-endian-actual-args.ll
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big-endian-call-result.ll
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big-endian-formal-args.ll
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bitcasts-direct-move.ll
[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic
2017-03-15 16:04:53 +00:00
blockaddress.ll
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BoolRetToIntTest-2.ll
[PPC] In PPCBoolRetToInt change the bool value to i64 if the target is ppc64
2017-06-08 18:27:24 +00:00
BoolRetToIntTest.ll
[PPC] In PPCBoolRetToInt change the bool value to i64 if the target is ppc64
2017-06-08 18:27:24 +00:00
bperm.ll
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branch_coalesce.ll
Improve scheduling with branch coalescing
2017-03-01 20:29:34 +00:00
branch-hint.ll
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branch-opt.ll
Codegen: Tail-duplicate during placement.
2016-10-11 20:36:43 +00:00
BreakableToken-reduced.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
bswap-load-store.ll
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build-vector-tests.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
buildvec_canonicalize.ll
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builtins-ppc-elf2-abi.ll
[PowerPC] Add vector conversion builtins to altivec.h - LLVM portion
2016-11-11 14:41:19 +00:00
builtins-ppc-p8vector.ll
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bv-pres-v8i1.ll
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bv-widen-undef.ll
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byval-agg-info.ll
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byval-aliased.ll
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calls.ll
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can-lower-ret.ll
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cannonicalize-vector-shifts.ll
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cc.ll
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change-no-infs.ll
[TM] Restore default TargetOptions in TargetMachine::resetTargetOptions.
2017-01-10 23:43:04 +00:00
cmp-cmp.ll
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cmpb-ppc32.ll
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cmpb.ll
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coal-sections.ll
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coalesce-ext.ll
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code-align.ll
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combine-to-pre-index-store-crash.ll
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compare-duplicate.ll
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compare-simm.ll
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complex-return.ll
Update constants in complex-return test to prevent reduction to smaller constants
2017-06-24 01:29:24 +00:00
constants-i64.ll
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constants.ll
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copysignl.ll
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cr1eq-no-extra-moves.ll
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cr1eq.ll
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cr_spilling.ll
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cr-spills.ll
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crash.ll
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crbit-asm-disabled.ll
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crbit-asm.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
crbits.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
crsave.ll
[PPC] Claim stack frame before storing into it, if no red zone is present
2016-09-06 12:30:00 +00:00
crypto_bifs.ll
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ctr-cleanup.ll
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ctr-loop-tls-const.ll
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ctr-minmaxnum.ll
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ctrloop-asm.ll
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ctrloop-cpsgn.ll
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ctrloop-fp64.ll
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ctrloop-i64.ll
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ctrloop-i128.ll
[PowerPC] multiply-with-overflow might use the CTR register
2017-04-11 02:03:17 +00:00
ctrloop-intrin.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
ctrloop-large-ec.ll
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ctrloop-le.ll
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ctrloop-lt.ll
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ctrloop-ne.ll
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ctrloop-reg.ll
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ctrloop-s000.ll
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ctrloop-sh.ll
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ctrloop-sums.ll
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ctrloop-udivti3.ll
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ctrloops-softfloat.ll
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ctrloops.ll
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cttz.ll
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cxx_tlscc64.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
darwin-labels.ll
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dbg.ll
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DbgValueOtherTargets.test
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dcbt-sched.ll
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delete-node.ll
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direct-move-profit.ll
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div-2.ll
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div-e-32.ll
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div-e-all.ll
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dyn-alloca-aligned.ll
RegScavenging: Add scavengeRegisterBackwards()
2017-06-17 02:08:18 +00:00
dyn-alloca-offset.ll
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e500-1.ll
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early-ret2.ll
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early-ret.ll
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ec-input.ll
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eh-dwarf-cfa.ll
Add ISD::EH_DWARF_CFA, simplify @llvm.eh.dwarf.cfa on Mips, fix on PowerPC
2016-09-01 10:28:47 +00:00
empty-functions.ll
Don't emit CFI instructions at the end of a function
2017-04-24 18:45:59 +00:00
emptystruct.ll
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emutls_generic.ll
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eqv-andc-orc-nor.ll
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expand-contiguous-isel.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-1.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-2.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-3.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-4.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-5.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-6.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-7.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel-8.mir
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
expand-isel.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
ext-bool-trunc-repl.ll
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extra-toc-reg-deps.ll
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extsh.ll
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f32-to-i64.ll
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fabs.ll
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fast-isel-binary.ll
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fast-isel-br-const.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
fast-isel-call.ll
[PowerPC] Zero-extend constants in FastISel
2016-09-04 06:07:19 +00:00
fast-isel-cmp-imm.ll
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fast-isel-const.ll
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fast-isel-conversion-p5.ll
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fast-isel-conversion.ll
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fast-isel-crash.ll
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fast-isel-ext.ll
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fast-isel-fcmp-nan.ll
[PPC] Generate positive FP zero using xor insn instead of loading from constant area
2016-10-24 17:31:09 +00:00
fast-isel-fold.ll
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fast-isel-fpconv.ll
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fast-isel-GEP-coalesce.ll
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fast-isel-i64offset.ll
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fast-isel-icmp-split.ll
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fast-isel-indirectbr.ll
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fast-isel-load-store-vsx.ll
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fast-isel-load-store.ll
Use shouldAssumeDSOLocal in classifyGlobalReference.
2017-01-26 15:02:31 +00:00
fast-isel-redefinition.ll
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fast-isel-ret.ll
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fast-isel-shifter.ll
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fastisel-gep-promote-before-add.ll
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fcpsgn.ll
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fdiv-combine.ll
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float-asmprint.ll
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float-to-int.ll
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
2016-10-04 11:25:52 +00:00
floatPSA.ll
[PowerPC] set optimization level in SelectionDAGISel
2017-06-27 04:52:17 +00:00
flt-preinc.ll
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fma-aggr-FMF.ll
[DAGCombiner] Initial support for the fast-math flag contract
2017-03-30 18:53:04 +00:00
fma-assoc.ll
[DAGCombine] require UnsafeFPMath for re-association of addition
2017-01-31 14:35:37 +00:00
fma-ext.ll
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fma-mutate-duplicate-vreg.ll
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fma-mutate-register-constraint.ll
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fma-mutate.ll
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fma.ll
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fmaxnum.ll
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fminnum.ll
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fnabs.ll
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fneg.ll
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fold-li.ll
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fold-zero.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
fp2int2fp-ppcfp128.ll
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fp64-to-int16.ll
[Legalizer] Fix fp-to-uint to fp-tosint promotion assertion.
2017-01-04 22:11:42 +00:00
fp128-bitcast-after-operation.ll
[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic
2017-03-15 16:04:53 +00:00
fp_to_uint.ll
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fp-branch.ll
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fp-int-conversions-direct-moves.ll
[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic
2017-03-15 16:04:53 +00:00
fp-int-fp.ll
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fp-to-int-ext.ll
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fp-to-int-to-fp.ll
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fpcopy.ll
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frame-size.ll
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frameaddr.ll
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Frames-alloca.ll
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Frames-large.ll
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Frames-leaf.ll
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Frames-small.ll
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frounds.ll
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fsel.ll
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fsl-e500mc.ll
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fsl-e5500.ll
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fsqrt.ll
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func-addr-consts.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
func-addr.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
glob-comp-aa-crash.ll
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hello-reloc.s
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hello.ll
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hidden-vis-2.ll
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hidden-vis.ll
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htm.ll
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i1-ext-fold.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
i1-to-double.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
i32-to-float.ll
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i64_fp_round.ll
[PowerPC] Use rldicr instruction for AND with an immediate if possible
2017-02-24 18:03:16 +00:00
i64_fp.ll
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i64-to-float.ll
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
2016-10-04 11:25:52 +00:00
i128-and-beyond.ll
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ia-mem-r0.ll
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ia-neg-const.ll
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iabs.ll
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ifcvt-forked-bug-2016-08-08.ll
CodeGen: If Convert blocks that would form a diamond when tail-merged.
2016-08-24 21:34:27 +00:00
ifcvt.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
illegal-element-type.ll
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in-asm-f64-reg.ll
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indexed-load.ll
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indirect-hidden.ll
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indirectbr.ll
[CGP] Split some critical edges coming out of indirect branches
2017-02-28 00:11:34 +00:00
inline-asm-s-modifier.ll
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inline-asm-scalar-to-vector-error.ll
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
2016-10-04 06:59:23 +00:00
inlineasm-copy.ll
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inlineasm-i64-reg.ll
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int-fp-conv-0.ll
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int-fp-conv-1.ll
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inverted-bool-compares.ll
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isel-rc-nox0.ll
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isel.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
ispositive.ll
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itofp128.ll
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jaggedstructs.ll
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
2017-03-14 00:34:14 +00:00
LargeAbsoluteAddr.ll
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lbz-from-ld-shift.ll
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lbzux.ll
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ld-st-upd.ll
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ldtoc-inv.ll
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lha.ll
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licm-remat.ll
[PowerPC] define target hook isReallyTriviallyReMaterializable()
2017-06-21 17:17:56 +00:00
licm-tocReg.ll
[MachineLICM] Hoist TOC-based address instructions
2017-06-15 18:29:59 +00:00
lit.local.cfg
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livephysregs.mir
LivePhysRegs: Fix addLiveOutsNoPristines() for return blocks past PEI
2017-05-26 16:23:08 +00:00
load-constant-addr.ll
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load-shift-combine.ll
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load-two-flts.ll
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load-v4i8-improved.ll
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
2016-10-04 06:59:23 +00:00
logic-ops-on-compares.ll
Revert r304907 as it is causing some failures that I cannot reproduce.
2017-06-14 07:05:42 +00:00
long-compare.ll
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longcall.ll
[PowerPC] Add support for -mlongcall
2016-08-30 00:59:23 +00:00
longdbl-truncate.ll
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loop-data-prefetch-inner.ll
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loop-data-prefetch.ll
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loop-prep-all.ll
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lsa.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
lsr-postinc-pos.ll
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lxvw4x-bug.ll
[Power9] Add exploitation of non-permuting memory ops
2016-09-22 09:52:19 +00:00
machine-combiner.ll
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
2016-10-04 06:59:23 +00:00
mask64.ll
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mature-mc-support.ll
[LLC] Add an inline assembly diagnostics handler.
2017-02-03 11:14:39 +00:00
mc-instrlat.ll
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mcm-1.ll
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mcm-2.ll
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mcm-3.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
mcm-4.ll
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
2016-10-04 11:25:52 +00:00
mcm-5.ll
Always use relative jump table encodings on PowerPC64.
2016-11-16 00:37:30 +00:00
mcm-6.ll
…
mcm-7.ll
…
mcm-8.ll
…
mcm-9.ll
…
mcm-10.ll
…
mcm-11.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
mcm-12.ll
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
2016-10-04 11:25:52 +00:00
mcm-13.ll
…
mcm-default.ll
…
mcm-obj-2.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
mcm-obj.ll
Use shouldAssumeDSOLocal in classifyGlobalReference.
2017-01-26 15:02:31 +00:00
mcount-insertion.ll
Add a counter-function insertion pass
2016-09-01 09:42:39 +00:00
mem_update.ll
…
mem-rr-addr-mode.ll
…
memcmp.ll
[PowerPC] auto-generate check lines; NFC
2017-06-30 19:20:54 +00:00
memcmpIR.ll
[CGP] add specialization for memcmp expansion with only one basic block
2017-06-27 23:15:01 +00:00
memCmpUsedInZeroEqualityComparison.ll
[CGP] eliminate a sub instruction in memcmp expansion
2017-06-27 21:46:34 +00:00
memcpy_dereferenceable.ll
[SelectionDAG] set dereferenceable flag when expanding memcpy/memmove
2017-06-24 15:17:38 +00:00
memcpy-vec.ll
…
memset-nc-le.ll
…
memset-nc.ll
…
merge_stores_dereferenceable.ll
[SelectionDAG] set dereferenceable flag in MergeConsecutiveStores to fix assetion failure
2017-06-27 12:43:08 +00:00
merge-st-chain-op.ll
…
MergeConsecutiveStores.ll
…
mftb.ll
…
misched-inorder-latency.ll
CodeGen: Allow small copyable blocks to "break" the CFG.
2017-01-31 23:48:32 +00:00
misched.ll
…
mtvsrdd.ll
[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0
2017-05-11 22:17:35 +00:00
mul-neg-power-2.ll
…
mul-with-overflow.ll
…
mulhs.ll
…
mulli64.ll
…
mult-alt-generic-powerpc64.ll
…
mult-alt-generic-powerpc.ll
…
multi-return.ll
…
named-reg-alloc-r0.ll
…
named-reg-alloc-r1-64.ll
…
named-reg-alloc-r1.ll
…
named-reg-alloc-r2-64.ll
…
named-reg-alloc-r2.ll
…
named-reg-alloc-r13-64.ll
…
named-reg-alloc-r13.ll
…
neg.ll
…
negate-i1.ll
[DAG] optimize negation of bool
2016-10-19 16:58:59 +00:00
negctr.ll
…
no-dead-strip.ll
…
no-dup-spill-fp.ll
[PowerPC] Don't spill the frame pointer twice
2016-08-31 00:52:03 +00:00
no-ext-with-count-zeros.ll
[PowerPC] - No SExt/ZExt needed for count trailing zeros
2016-10-27 05:17:58 +00:00
no-extra-fp-conv-ldst.ll
…
no-pref-jumps.ll
…
no-rlwimi-trivial-commute.mir
MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing it
2016-08-24 22:34:06 +00:00
novrsave.ll
…
opt-cmp-inst-cr0-live.ll
Summary
2017-05-21 06:00:05 +00:00
opt-sub-inst-cr0-live.mir
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
2016-08-25 01:27:13 +00:00
optcmp.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
optnone-crbits-i1-ret.ll
…
or-addressing-mode.ll
…
p8-isel-sched.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
p8-scalar_vector_conversions.ll
[PowerPC][Altivec] Add mfvrd and mffprd extended mnemonic
2017-03-15 16:04:53 +00:00
p8altivec-shuffles-pred.ll
[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
p9-vector-compares-and-counts.ll
Implement vector count leading/trailing bytes with zero lsb and vector parity
2016-10-28 19:38:24 +00:00
p9-xxinsertw-xxextractuw.ll
[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
peephole-align.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
pie.ll
…
pip-inner.ll
…
popcnt.ll
…
post-ra-ec.ll
…
power9-moves-and-splats.ll
[Power9] Allow AnyExt immediates for XXSPLTIB
2016-12-15 11:16:20 +00:00
ppc32-align-long-double-sf.ll
…
ppc32-constant-BE-ppcf128.ll
…
ppc32-cyclecounter.ll
…
ppc32-i1-vaarg.ll
…
ppc32-lshrti3.ll
…
ppc32-nest.ll
…
ppc32-pic-large.ll
[PPC] Set SP after loading data from stack frame, if no red zone is present
2016-09-22 17:22:43 +00:00
ppc32-pic.ll
[PPC] Set SP after loading data from stack frame, if no red zone is present
2016-09-22 17:22:43 +00:00
ppc32-skip-regs.ll
…
ppc32-vacopy.ll
…
ppc64-32bit-addic.ll
…
ppc64-abi-extend.ll
…
ppc64-align-long-double.ll
[PowerPC] set optimization level in SelectionDAGISel
2017-06-27 04:52:17 +00:00
ppc64-altivec-abi.ll
…
ppc64-anyregcc-crash.ll
…
ppc64-anyregcc.ll
[StackMaps] Increase the size of the "location size" field
2017-04-28 04:48:42 +00:00
ppc64-blnop.ll
[PowerPC] Fix logic dealing with nop after calls (and tail-call eligibility)
2017-01-04 21:05:13 +00:00
ppc64-byval-align.ll
…
ppc64-calls.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
ppc64-crash.ll
…
ppc64-cyclecounter.ll
…
ppc64-elf-abi.ll
…
ppc64-fastcc-fast-isel.ll
…
ppc64-fastcc.ll
…
ppc64-func-desc-hoist.ll
…
ppc64-gep-opt.ll
Turn on -addr-sink-using-gep by default.
2017-04-06 22:42:18 +00:00
ppc64-get-cache-line-size.ll
[PowerPC] Correctly specify the cache line size for Power 7, 8 and 9.
2017-05-31 18:20:17 +00:00
ppc64-i128-abi.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
ppc64-icbt-pwr7.ll
…
ppc64-icbt-pwr8.ll
…
ppc64-linux-func-size.ll
…
ppc64-nest.ll
…
ppc64-nonfunc-calls.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
ppc64-P9-mod.ll
[Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.
2017-06-12 17:58:42 +00:00
ppc64-patchpoint.ll
…
ppc64-prefetch.ll
…
ppc64-r2-alloc.ll
…
ppc64-sibcall-shrinkwrap.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
ppc64-sibcall.ll
[PowerPC] Fix logic dealing with nop after calls (and tail-call eligibility)
2017-01-04 21:05:13 +00:00
ppc64-smallarg.ll
…
ppc64-stackmap-nops.ll
…
ppc64-stackmap.ll
[StackMaps] Increase the size of the "location size" field
2017-04-28 04:48:42 +00:00
ppc64-toc.ll
…
ppc64-vaarg-int.ll
…
ppc64-zext.ll
…
ppc64le-aggregates.ll
[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combine
2017-03-01 18:12:29 +00:00
ppc64le-calls.ll
…
ppc64le-crsave.ll
…
ppc64le-localentry-large.ll
…
ppc64le-localentry.ll
…
ppc64le-smallarg.ll
[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
2017-07-10 16:44:45 +00:00
ppc440-fp-basic.ll
…
ppc440-msync.ll
…
ppc-crbits-onoff.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
ppc-ctr-dead-code.ll
[PowerPC] Make sure that we remove dead PHI nodes after the PPCCTRLoops pass.
2017-07-05 17:57:57 +00:00
ppc-empty-fs.ll
…
ppc-prologue.ll
…
ppc-redzone-alignment-bug.ll
[PPC] Fix two bugs in frame lowering.
2017-07-11 16:42:20 +00:00
ppc-shrink-wrapping.ll
Fix some broken CHECK lines.
2017-01-22 20:28:56 +00:00
ppc-vaarg-agg.ll
…
ppcf128-1-opt.ll
…
ppcf128-1.ll
…
ppcf128-2.ll
…
ppcf128-3.ll
…
ppcf128-4.ll
…
ppcf128-endian.ll
…
ppcf128sf.ll
Elide stores which are overwritten without being observed.
2017-05-16 19:43:56 +00:00
ppcsoftops.ll
[PowerPC] Refactor soft-float support, and enable PPC64 soft float
2016-10-02 02:10:20 +00:00
pr3711_widen_bit.ll
…
pr12757.ll
…
pr13641.ll
…
pr13891.ll
…
pr15031.ll
…
pr15359.ll
…
pr15630.ll
…
pr15632.ll
…
pr16556-2.ll
…
pr16556.ll
…
pr16573.ll
…
pr17168.ll
Renumber testcase metadata nodes after r290153.
2016-12-22 00:45:21 +00:00
pr17354.ll
…
pr18663-2.ll
…
pr18663.ll
…
pr20442.ll
…
pr22711.ll
…
pr24216.ll
…
pr24546.ll
[IR] Remove the DIExpression field from DIGlobalVariable.
2016-12-20 02:09:43 +00:00
pr24636.ll
…
pr25157-peephole.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
pr25157.ll
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
2016-10-04 11:25:52 +00:00
pr26180.ll
…
pr26193.ll
…
pr26356.ll
…
pr26378.ll
…
pr26381.ll
…
pr26617.ll
…
pr26690.ll
…
pr27078.ll
[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
pr27350.ll
…
pr28130.ll
…
pr28630.ll
…
pr30451.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
pr30640.ll
PowerPC: specify full triple to avoid different Darwin asm syntax.
2016-10-14 21:25:29 +00:00
pr30663.ll
[PPCMIPeephole] Fix splat elimination
2016-10-12 00:48:25 +00:00
pr30715.ll
Do not assume that FP vector operands are never legalized by expanding
2016-10-26 19:51:35 +00:00
pr31144.ll
[PPC] Prefer direct move on power8 if load 1 or 2 bytes to VSR
2016-12-12 22:09:02 +00:00
pr32063.ll
[PPC] Fix code generation for bswap(int32) followed by store16
2017-03-02 21:07:59 +00:00
pr32140.ll
[PowerPC] Fix failure with STBRX when store is narrower than the bswap
2017-03-06 07:32:13 +00:00
pr33093.ll
[PPC CodeGen] Expand the bitreverse.i64 intrinsic.
2017-07-10 18:11:23 +00:00
PR33636.ll
Add the missing triple to the test case added as part of r307120.
2017-07-05 05:14:43 +00:00
PR33671.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
preinc-ld-sel-crash.ll
…
preincprep-invoke.ll
…
preincprep-nontrans-crash.ll
…
private.ll
…
pwr3-6x.ll
…
pwr7-gt-nop.ll
…
pzero-fp-xored.ll
[PPC] Adding the removed testcase again
2016-10-27 19:10:09 +00:00
qpx-bv-sint.ll
…
qpx-bv.ll
…
qpx-func-clobber.ll
…
qpx-load-splat.ll
…
qpx-load.ll
…
qpx-recipest.ll
…
qpx-rounding-ops.ll
…
qpx-s-load.ll
…
qpx-s-sel.ll
…
qpx-s-store.ll
…
qpx-sel.ll
…
qpx-split-vsetcc.ll
…
qpx-store.ll
…
qpx-unal-cons-lds.ll
…
qpx-unalperm.ll
…
quadint-return.ll
…
r31.ll
…
recipest.ll
[Target] move reciprocal estimate settings from TargetOptions to TargetLowering
2016-10-04 20:46:43 +00:00
reg-coalesce-simple.ll
…
reg-names.ll
…
reloc-align.ll
…
remap-crash.ll
…
remat-imm.ll
…
remove-redundant-moves.ll
…
resolvefi-basereg.ll
…
resolvefi-disp.ll
…
restore-r30.ll
[PPC] When restoring R30 (PIC base pointer), mark it as <def>
2017-05-04 19:14:54 +00:00
retaddr2.ll
…
retaddr.ll
…
return-val-i128.ll
…
rlwimi2.ll
…
rlwimi3.ll
…
rlwimi-and-or-bits.ll
…
rlwimi-and.ll
…
rlwimi-commute.ll
…
rlwimi-dyn-and.ll
…
rlwimi-keep-rsh.ll
…
rlwimi.ll
…
rlwinm2.ll
…
rlwinm-zero-ext.ll
…
rlwinm.ll
…
rm-zext.ll
…
rotl-2.ll
…
rotl-64.ll
…
rotl-rotr-crash.ll
…
rotl.ll
…
rounding-ops.ll
…
rs-undef-use.ll
…
s000-alias-misched.ll
…
save-bp.ll
[PPC] Properly update register save area offsets
2017-05-17 13:25:09 +00:00
save-cr-ppc32svr4.ll
[PPC] Properly update register save area offsets
2017-05-17 13:25:09 +00:00
save-crbp-ppc32svr4.ll
[PPC] Properly update register save area offsets
2017-05-17 13:25:09 +00:00
scavenging.mir
RegScavenging: Add scavengeRegisterBackwards()
2017-06-17 02:08:18 +00:00
sdag-ppcf128.ll
…
sdiv-pow2.ll
…
sections.ll
…
select_const.ll
[DAGCombiner] allow transforming (select Cond, C +/- 1, C) to (add(ext Cond), C)
2017-03-04 19:18:09 +00:00
select_lt0.ll
…
select-addrRegRegOnly.ll
[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
2017-07-10 16:44:45 +00:00
select-cc.ll
…
select-i1-vs-i1.ll
[PowerPC][Altivec] Add vmr extended mnemonic
2017-01-31 13:43:11 +00:00
selectiondag-extload-computeknownbits.ll
…
set0-v8i16.ll
…
setcc_no_zext.ll
…
setcc-logic.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
setcc-to-sub.ll
Do full codegen for various tests. NFC
2017-02-27 01:15:57 +00:00
setcclike-or-comb.ll
[DAGCombine] More fixups to SETCC legality checking (visitANDLike/visitORLike)
2016-09-06 23:02:23 +00:00
seteq-0.ll
…
shift128.ll
CodeGen: Power: Add lowering for shifts of v1i128.
2017-05-17 21:54:41 +00:00
shift_mask.ll
[PowerPC, DAGCombiner] Fold a << (b % (sizeof(a) * 8)) back to a single instruction
2017-05-03 00:07:02 +00:00
shift-cmp.ll
[PowerPC] Add a pattern for a runtime bit check
2016-09-02 02:34:44 +00:00
shl_elim.ll
…
shl_sext.ll
…
sign_ext_inreg1.ll
…
sj-ctr-loop.ll
…
sjlj_no0x.ll
[PowerPC] Fix sjlj pseduo instructions to use G8RC_NOX0 register class
2017-02-01 14:33:57 +00:00
sjlj.ll
Codegen: Tail-duplicate during placement.
2016-10-11 20:36:43 +00:00
small-arguments.ll
…
spill-nor0.ll
…
splat-bug.ll
…
split-index-tc.ll
…
srl-mask.ll
[PowerPC] Use rldicr instruction for AND with an immediate if possible
2017-02-24 18:03:16 +00:00
stack-no-redzone.ll
[PPC] Set SP after loading data from stack frame, if no red zone is present
2016-09-22 17:22:43 +00:00
stack-protector.ll
…
stack-realign.ll
[PPC] Set SP after loading data from stack frame, if no red zone is present
2016-09-22 17:22:43 +00:00
stackmap-frame-setup.ll
Add extra operand to CALLSEQ_START to keep frame part set up previously
2017-05-09 13:35:13 +00:00
stacksize.ll
Revert "Revert "[PowerPC][ELFv2ABI] Allocate parameter area on-demand to reduce stack frame size""
2017-03-08 02:41:35 +00:00
std-unal-fi.ll
…
stdux-constuse.ll
…
stfiwx-2.ll
…
stfiwx.ll
…
store-load-fwd.ll
…
store-update.ll
…
structsinmem.ll
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
2017-03-14 00:34:14 +00:00
structsinregs.ll
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
2017-03-14 00:34:14 +00:00
stubs.ll
…
stwu8.ll
…
stwu-gta.ll
…
stwux.ll
…
sub-bv-types.ll
…
subc.ll
…
subreg-postra-2.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
subreg-postra.ll
[PowerPC] Expand ISEL instruction into if-then-else sequence.
2017-01-16 20:12:26 +00:00
subtract_from_imm.ll
[PowerPC] Use subfic instruction for subtract from immediate
2017-02-24 18:16:06 +00:00
svr4-redzone.ll
[PPC] Fix two bugs in frame lowering.
2017-07-11 16:42:20 +00:00
swaps-le-1.ll
[PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LE
2017-05-02 01:47:34 +00:00
swaps-le-2.ll
[PowerPC] Emit VMX loads/stores for aligned ops to avoid adding swaps on LE
2017-05-02 01:47:34 +00:00
swaps-le-3.ll
…
swaps-le-4.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
swaps-le-5.ll
…
swaps-le-6.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
swaps-le-7.ll
[PPC] cleanup of mayLoad/mayStore flags and memory operands.
2017-01-26 18:59:15 +00:00
tail-dup-analyzable-fallthrough.ll
[PPC] Generate positive FP zero using xor insn instead of loading from constant area
2016-10-24 17:31:09 +00:00
tail-dup-branch-to-fallthrough.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
tail-dup-break-cfg.ll
Codegen: Make chains from trellis-shaped CFGs
2017-02-15 19:49:14 +00:00
tail-dup-layout.ll
CodeGen: BlockPlacement: Increase tail duplication size for O3.
2017-05-15 17:30:47 +00:00
tailcall1-64.ll
Specify complete target triple in test
2017-07-12 01:16:50 +00:00
tailcall1.ll
…
tailcall-string-rvo.ll
Use PIC relocation model as default for PowerPC64 ELF.
2016-12-15 00:01:53 +00:00
tailcallpic1.ll
…
testBitReverse.ll
[PPC CodeGen] Expand the bitreverse.i64 intrinsic.
2017-07-10 18:11:23 +00:00
testComparesieqsc.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesieqsi.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesieqsll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testComparesieqss.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesiequc.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesiequi.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesiequll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testComparesiequs.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesinesc.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesinesi.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesiness.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesineuc.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesineui.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testComparesineus.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-06-07 12:23:41 +00:00
testCompareslleqsc.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testCompareslleqsi.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testCompareslleqsll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testCompareslleqss.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesllequc.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesllequi.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
testComparesllequll.ll
[PowerPC] Eliminate integer compare instructions - vol. 3
2017-05-31 08:04:07 +00:00
testComparesllequs.ll
[PowerPC] Eliminate integer compare instructions - vol. 1
2017-05-11 16:54:23 +00:00
thread-pointer.ll
…
tls_get_addr_clobbers.ll
…
tls_get_addr_fence1.mir
[PowerPC] fix potential verification error on __tls_get_addr
2017-06-29 14:13:38 +00:00
tls_get_addr_fence2.mir
[PowerPC] fix potential verification error on __tls_get_addr
2017-06-29 14:13:38 +00:00
tls_get_addr_stackframe.ll
…
tls-cse.ll
…
tls-pic.ll
…
tls-store2.ll
…
tls.ll
[PowerPC] set optimization level in SelectionDAGISel
2017-06-27 04:52:17 +00:00
toc-load-sched-bug.ll
Add address space mangling to lifetime intrinsics
2017-04-10 20:18:21 +00:00
trampoline.ll
…
unal4-std.ll
…
unal-altivec2.ll
…
unal-altivec-wint.ll
…
unal-altivec.ll
…
unal-vec-ldst.ll
…
unal-vec-negarith.ll
…
unaligned.ll
…
unsafe-math.ll
…
unwind-dw2-g.ll
…
unwind-dw2.ll
…
vaddsplat.ll
…
varargs-struct-float.ll
…
varargs.ll
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variable_elem_vec_extracts.ll
DAG: Avoid OOB when legalizing vector indexing
2017-01-10 22:02:30 +00:00
vcmp-fold.ll
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vec_abs.ll
…
vec_absd.ll
Fix some broken CHECK lines.
2017-01-22 20:28:56 +00:00
vec_add_sub_doubleword.ll
…
vec_add_sub_quadword.ll
DAG: Fold out out of bounds insert_vector_elt
2016-12-03 23:03:26 +00:00
vec_auto_constant.ll
…
vec_br_cmp.ll
…
vec_buildvector_loadstore.ll
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vec_call.ll
…
vec_clz.ll
…
vec_cmp.ll
[PowerPC][Altivec] Add vnot extended mnemonic
2017-02-07 18:57:29 +00:00
vec_cmpd.ll
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vec_constants.ll
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vec_conv.ll
…
vec_extload.ll
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vec_extract_p9.ll
[Power9] Exploit vector extract with variable index.
2017-07-05 16:55:00 +00:00
vec_fmuladd.ll
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vec_fneg.ll
…
vec_insert.ll
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vec_int_ext.ll
[Power9] Exploit vector integer extend instructions when indices aren't correct.
2017-07-05 16:00:38 +00:00
vec_mergeow.ll
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vec_minmax.ll
…
vec_misaligned.ll
…
vec_mul_even_odd.ll
…
vec_mul.ll
…
vec_perf_shuffle.ll
…
vec_popcnt.ll
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vec_revb.ll
[PowerPC] Match vec_revb builtins to P9 instructions.
2017-06-12 18:24:36 +00:00
vec_rotate_shift.ll
…
vec_rounding.ll
…
vec_select.ll
…
vec_shift.ll
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vec_shuffle_le.ll
…
vec_shuffle_p8vector_le.ll
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vec_shuffle_p8vector.ll
…
vec_shuffle.ll
…
vec_sldwi.ll
[PowerPC] Fix a performance bug for PPC::XXSLDWI.
2017-05-24 23:48:29 +00:00
vec_splat_constant.ll
…
vec_splat.ll
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vec_sqrt.ll
…
vec_urem_const.ll
…
vec_veqv_vnand_vorc.ll
…
vec_vrsave.ll
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vec_xxpermdi.ll
[PowerPC] Fix a performance bug for PPC::XXPERMDI.
2017-05-31 13:09:57 +00:00
vec_zero.ll
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vec-abi-align.ll
…
vec-asm-disabled.ll
…
vector-identity-shuffle.ll
…
vector-merge-store-fp-constants.ll
…
vector.ll
…
vperm-instcombine.ll
…
vperm-lowering.ll
…
vrsave-spill.ll
…
vrspill.ll
…
vsel-prom.ll
…
vsx_insert_extract_le.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx_scalar_ld_st.ll
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
2016-10-04 11:25:52 +00:00
vsx_shuffle_le.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx-args.ll
[PowerPC][Altivec] Add vmr extended mnemonic
2017-01-31 13:43:11 +00:00
VSX-DForm-Scalars.ll
[Power9] Exploit D-Form VSX Scalar memory ops that target full VSX register set
2016-10-04 11:25:52 +00:00
vsx-div.ll
…
vsx-elementary-arith.ll
…
vsx-fma-m.ll
…
vsx-fma-mutate-trivial-copy.ll
…
vsx-fma-mutate-undef.ll
…
vsx-fma-sp.ll
…
vsx-infl-copy1.ll
[PowerPC][Altivec] Add vmr extended mnemonic
2017-01-31 13:43:11 +00:00
vsx-infl-copy2.ll
…
vsx-ldst-builtin-le.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx-ldst.ll
P9: D-form vector load/store. Differential Revision: https://reviews.llvm.org/D33248
2017-05-24 17:50:37 +00:00
vsx-minmax.ll
…
vsx-p8.ll
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
2016-10-04 06:59:23 +00:00
vsx-p9.ll
[PowerPC] Ensure displacements for DQ-Form instructions are multiples of 16
2017-07-13 18:17:10 +00:00
vsx-partword-int-loads-and-stores.ll
[PowerPC] Reduce register pressure by not materializing a constant just for use as an index register for X-Form loads/stores.
2017-07-10 16:44:45 +00:00
vsx-recip-est.ll
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vsx-self-copy.ll
…
vsx-spill-norwstore.ll
[Power9] Part-word VSX integer scalar loads/stores and sign extend instructions
2016-10-04 06:59:23 +00:00
vsx-spill.ll
RegisterScavenging: Followup to r305625
2017-06-20 18:43:14 +00:00
vsx-vec-spill.ll
Fix a test case failure on Apple PPC.
2016-10-04 07:37:38 +00:00
vsx-word-splats.ll
…
vsx.ll
RegisterScavenging: Followup to r305625
2017-06-20 18:43:14 +00:00
vtable-reloc.ll
…
weak_def_can_be_hidden.ll
…
xvcmpeqdp-v2f64.ll
…
xxleqv_xxlnand_xxlorc.ll
…
zero-not-run.ll
…
zext-free.ll
…