Max Kazantsev 2c627a97fd [IRCE] Recognize loops with ne/eq latch conditions ...

In some particular cases eq/ne conditions can be turned into equivalent
slt/sgt conditions. This patch teaches parseLoopStructure to handle some
of these cases.

Differential Revision: https://reviews.llvm.org/D35010

llvm-svn: 308264

2017-07-18 04:53:48 +00:00

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add-metadata-pre-post-loops.ll

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bad-loop-structure.ll

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bug-loop-varying-upper-limit.ll

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bug-mismatched-types.ll

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conjunctive-checks.ll

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correct-loop-info.ll

[IRCE] Canonicalize pre/post loops after the blocks are added into parent loop

2017-06-06 14:54:01 +00:00

decrementing-loop.ll

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eq_ne.ll

[IRCE] Recognize loops with ne/eq latch conditions

2017-07-18 04:53:48 +00:00

low-becount.ll

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multiple-access-no-preloop.ll

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not-likely-taken.ll

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only-lower-check.ll

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only-upper-check.ll

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pre_post_loops.ll

[IRCE] Fix corner case with Start = INT_MAX

2017-07-14 06:35:03 +00:00

single-access-no-preloop.ll

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single-access-with-preloop.ll

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skip-profitability-checks.ll

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unhandled.ll

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with-parent-loops.ll

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