Garvit Gupta 062844615d [RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287) ...

This PR is a follow-up of PR #96174 which added the framework to resolve
encoding conflicts among vendor specific CSRs. This PR explicitly
enables this only for the RISCV target.

2024-07-11 20:12:17 -07:00

..

AsmParser

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287)

2024-07-11 20:12:17 -07:00

Disassembler

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

GISel

[GISel] Make create.*InstructionSelector arguments const (#98243)

2024-07-10 09:01:27 -04:00

MCA

[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc

2024-04-24 09:29:20 -07:00

MCTargetDesc

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287)

2024-07-11 20:12:17 -07:00

TargetInfo

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CMakeLists.txt

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)

2024-07-11 14:22:00 +08:00

RISCV.h

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)

2024-07-11 14:22:00 +08:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR3 (#95427)

2024-06-25 11:34:59 +03:00

RISCVAsmPrinter.cpp

[IR] Don't include Module.h in Analysis.h (NFC) (#97023)

2024-06-28 14:30:47 +02:00

RISCVCallingConv.td

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RISCVCodeGenPrepare.cpp

Revert "[RISCV] Expand vp.stride.load to splat of a scalar load." (#98422)

2024-07-10 20:54:41 -04:00

RISCVCombine.td

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RISCVDeadRegisterDefinitions.cpp

[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)

2024-07-10 19:34:48 +08:00

RISCVExpandAtomicPseudoInsts.cpp

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RISCVExpandPseudoInsts.cpp

[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)

2024-04-16 15:40:32 -07:00

RISCVFeatures.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

RISCVFrameLowering.cpp

[RISCV] Remove getOffsetOfLocalArea() (#93765)

2024-06-17 15:38:37 +08:00

RISCVFrameLowering.h

[RISCV] Add CFI information for vector callee-saved registers (#86811)

2024-04-17 10:42:40 +08:00

RISCVGatherScatterLowering.cpp

[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)

2024-06-28 08:36:49 +02:00

RISCVGISel.td

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RISCVInsertReadWriteCSR.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

RISCVInsertVSETVLI.cpp

[RISCV] Fix coalesced vsetvli's AVL LiveInterval not always being shrunk (#98286)

2024-07-12 09:40:20 +08:00

RISCVInsertWriteVXRM.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

RISCVInstrFormats.td

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RISCVInstrFormatsC.td

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RISCVInstrFormatsV.td

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RISCVInstrGISel.td

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RISCVInstrInfo.cpp

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

RISCVInstrInfo.h

[RISCV] Rematerialize vid.v (#97520)

2024-07-04 11:34:25 +08:00

RISCVInstrInfo.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

RISCVInstrInfoA.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

RISCVInstrInfoC.td

[RISCV] Fix 0-offset aliases for compressed sp-based opcodes (#98034)

2024-07-10 14:33:15 +01:00

RISCVInstrInfoD.td

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

2024-06-21 08:34:04 +02:00

RISCVInstrInfoF.td

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

2024-06-21 08:34:04 +02:00

RISCVInstrInfoM.td

[RISCV] Make M imply Zmmul (#95070)

2024-06-21 11:11:10 +08:00

RISCVInstrInfoSFB.td

…

RISCVInstrInfoV.td

[RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (#92768)

2024-05-23 12:10:46 -04:00

RISCVInstrInfoVPseudos.td

[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)

2024-07-10 10:51:20 +08:00

RISCVInstrInfoVSDPatterns.td

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

2024-06-21 08:34:04 +02:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Support vXf16 vector_shuffle with Zvfhmin. (#97491)

2024-07-03 23:56:17 -07:00

RISCVInstrInfoXCV.td

[RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P (#85603)

2024-07-04 01:25:10 +10:00

RISCVInstrInfoXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093)

2024-04-16 13:55:45 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Move strength reduction of mul X, 3/5/9*2^N to combine (#89966)

2024-05-08 10:13:01 -07:00

RISCVInstrInfoXVentana.td

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RISCVInstrInfoXwch.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

RISCVInstrInfoZa.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

RISCVInstrInfoZalasr.td

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RISCVInstrInfoZb.td

[RISCV] Rework zext.h handling for Zbkb again. (#96957)

2024-06-27 21:35:33 -07:00

RISCVInstrInfoZc.td

[RISCV] Make M imply Zmmul (#95070)

2024-06-21 11:11:10 +08:00

RISCVInstrInfoZcmop.td

[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)

2024-04-15 22:33:14 -07:00

RISCVInstrInfoZfa.td

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RISCVInstrInfoZfbfmin.td

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RISCVInstrInfoZfh.td

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RISCVInstrInfoZicbo.td

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RISCVInstrInfoZicfiss.td

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RISCVInstrInfoZicond.td

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RISCVInstrInfoZimop.td

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RISCVInstrInfoZk.td

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RISCVInstrInfoZvfbf.td

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RISCVInstrInfoZvk.td

[RISCV] Remove unused defaults for sew paramters in tablegen. NFC

2024-06-07 23:15:53 -07:00

RISCVISelDAGToDAG.cpp

[RISCV] Allow folding vmerge into masked ops when mask is the same (#97989)

2024-07-09 12:12:02 +08:00

RISCVISelDAGToDAG.h

[RISCV] Codegen support for XCVmem extension (#76916)

2024-06-07 21:45:49 +08:00

RISCVISelLowering.cpp

[RISCV] Reorder shuffle operands if one side is an identity (#98534)

2024-07-11 13:52:41 -07:00

RISCVISelLowering.h

[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)

2024-06-20 07:27:07 +02:00

RISCVMachineFunctionInfo.cpp

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RISCVMachineFunctionInfo.h

[llvm-project] Fix typo "seperate" (#95373)

2024-06-13 20:20:27 +01:00

RISCVMacroFusion.td

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RISCVMakeCompressible.cpp

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RISCVMergeBaseOffset.cpp

[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)

2024-05-28 15:05:23 -07:00

RISCVMoveMerger.cpp

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RISCVOptWInstrs.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Remove unneeded code from RISCVPostRAExpandPseudo::expandMovImm. NFC

2024-06-27 18:42:27 -07:00

RISCVProcessors.td

[RISCV] Reverse default assumption about performance of vlseN.v vd, (rs1), x0 (#98205)

2024-07-10 07:35:56 -07:00

RISCVProfiles.td

[RISCV] Gate unratified profiles behind -menable-experimental-extensions (#92167)

2024-05-15 21:09:43 +01:00

RISCVPushPopOptimizer.cpp

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RISCVRedundantCopyElimination.cpp

[RISCV] Codegen support for XCVbi extension (#89719)

2024-05-08 11:22:16 +08:00

RISCVRegisterInfo.cpp

[RISCV] Mark all registers marked isConstant as reserved (#96002)

2024-06-23 15:44:41 -07:00

RISCVRegisterInfo.h

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RISCVRegisterInfo.td

[RISCV] Use software guarded branch for indirect jump table branch. (#66762)

2024-05-14 14:44:25 +08:00

RISCVSchedRocket.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSchedSiFive7.td

[RISCV] Do not check PostRAScheduler in enablePostRAScheduler (#92781)

2024-05-24 14:31:14 -04:00

RISCVSchedSiFiveP400.td

[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)

2024-05-30 08:47:27 -07:00

RISCVSchedSiFiveP600.td

[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)

2024-05-30 08:47:27 -07:00

RISCVSchedSyntacoreSCR1.td

[RISCV][NFC] Cleanup SCR1 sched model (#96088)

2024-06-20 18:14:09 +03:00

RISCVSchedSyntacoreSCR3.td

[RISCV] Add scheduling model for Syntacore SCR3 (#95427)

2024-06-25 11:34:59 +03:00

RISCVSchedule.td

[RISCV][NFC] Add UnsupportedSched<F|D|A> multiclasses (#95948)

2024-06-19 12:37:47 +03:00

RISCVScheduleV.td

[RISCV] Split sched classes for vrgather.vv and vrgatherei16.vv (#92768)

2024-05-23 12:10:46 -04:00

RISCVScheduleXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093)

2024-04-16 13:55:45 +08:00

RISCVScheduleZb.td

…

RISCVScheduleZvk.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSubtarget.cpp

[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC (#98375)

2024-07-10 14:17:56 -07:00

RISCVSubtarget.h

[RISCV] Store a std::unique_ptr<RISCVRegisterBankInfo> in RISCVSubtarget. NFC (#98375)

2024-07-10 14:17:56 -07:00

RISCVSystemOperands.td

[RISCV] Enable framework to resolve encoding conflicts among vendor-specific CSRs (#97287)

2024-07-11 20:12:17 -07:00

RISCVTargetMachine.cpp

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)

2024-07-11 14:22:00 +08:00

RISCVTargetMachine.h

[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082)

2024-07-02 18:48:28 -07:00

RISCVTargetObjectFile.cpp

[IR] Don't include Module.h in Analysis.h (NFC) (#97023)

2024-06-28 14:30:47 +02:00

RISCVTargetObjectFile.h

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RISCVTargetTransformInfo.cpp

[RISCV][TTI] Add cost of type based binOp VP intrinsics with functionalOPC. (#93435)

2024-07-05 08:13:18 +08:00

RISCVTargetTransformInfo.h

Revert "[RISCV] Enable TTI::shouldDropLSRSolutionIfLessProfitable by default" (#98328)

2024-07-10 15:33:20 +01:00

RISCVVectorPeephole.cpp

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)

2024-07-11 14:22:00 +08:00