38200e94f1
Always try to fold freeze(op(....)) -> op(freeze(),freeze(),freeze(),...). This patch proposes we drop the opt-in limit for opcodes that are allowed to push a freeze through the op to freeze all its operands, through the tree towards the roots. I'm struggling to find a strong reason for this limit apart from the DAG freeze handling being immature for so long - as we've improved coverage in canCreateUndefOrPoison/isGuaranteedNotToBeUndefOrPoison it looks like the regressions are not as severe. Hopefully this will help some of the regression issues in #143102 etc.
164 lines
6.9 KiB
LLVM
164 lines
6.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=s390x-ibm-linux | FileCheck %s
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%struct.anon.0.1.2.3.8.77 = type { [3 x i8], i8, [3 x i8] }
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@e = external dso_local local_unnamed_addr global i32, align 4
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@f = external dso_local local_unnamed_addr global %struct.anon.0.1.2.3.8.77, align 4
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@g = external dso_local local_unnamed_addr global i8, align 2
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; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: readwrite)
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declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture) #0
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define dso_local void @m() local_unnamed_addr #1 {
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; CHECK-LABEL: m:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stmg %r13, %r15, 104(%r15)
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; CHECK-NEXT: aghi %r15, -168
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; CHECK-NEXT: lhrl %r1, f+4
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; CHECK-NEXT: larl %r2, f
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; CHECK-NEXT: llc %r2, 6(%r2)
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; CHECK-NEXT: larl %r3, e
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; CHECK-NEXT: lb %r0, 3(%r3)
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; CHECK-NEXT: rosbg %r2, %r1, 32, 55, 8
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; CHECK-NEXT: vlvgp %v0, %r2, %r0
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; CHECK-NEXT: vlvgf %v0, %r2, 0
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; CHECK-NEXT: vlvgf %v0, %r2, 2
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; CHECK-NEXT: vlvgp %v1, %r0, %r2
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; CHECK-NEXT: vlvgp %v2, %r2, %r2
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; CHECK-NEXT: lr %r1, %r2
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; CHECK-NEXT: nilh %r1, 255
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; CHECK-NEXT: chi %r1, 128
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; CHECK-NEXT: ipm %r1
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; CHECK-NEXT: risbg %r1, %r1, 63, 191, 36
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; CHECK-NEXT: vgbm %v3, 30583
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; CHECK-NEXT: vn %v0, %v0, %v3
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; CHECK-NEXT: vlvgf %v1, %r0, 0
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; CHECK-NEXT: vlvgf %v1, %r0, 2
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; CHECK-NEXT: vn %v1, %v1, %v3
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; CHECK-NEXT: vrepf %v2, %v2, 1
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; CHECK-NEXT: vn %v2, %v2, %v3
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; CHECK-NEXT: vrepif %v3, 127
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; CHECK-NEXT: vchlf %v0, %v0, %v3
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; CHECK-NEXT: vlgvf %r13, %v0, 0
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; CHECK-NEXT: vchlf %v2, %v2, %v3
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; CHECK-NEXT: vlgvf %r3, %v2, 1
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; CHECK-NEXT: nilf %r3, 1
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; CHECK-NEXT: vlgvf %r4, %v2, 0
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; CHECK-NEXT: risbg %r2, %r4, 48, 176, 15
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; CHECK-NEXT: rosbg %r2, %r3, 32, 49, 14
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; CHECK-NEXT: vlgvf %r5, %v2, 2
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; CHECK-NEXT: nilf %r5, 1
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; CHECK-NEXT: rosbg %r2, %r5, 32, 50, 13
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; CHECK-NEXT: vlgvf %r14, %v2, 3
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; CHECK-NEXT: nilf %r14, 1
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; CHECK-NEXT: rosbg %r2, %r14, 32, 51, 12
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; CHECK-NEXT: rosbg %r2, %r13, 52, 52, 11
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; CHECK-NEXT: vlgvf %r13, %v0, 1
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; CHECK-NEXT: rosbg %r2, %r13, 53, 53, 10
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; CHECK-NEXT: vlgvf %r13, %v0, 2
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; CHECK-NEXT: rosbg %r2, %r13, 54, 54, 9
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; CHECK-NEXT: vlgvf %r13, %v0, 3
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; CHECK-NEXT: rosbg %r2, %r13, 55, 55, 8
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; CHECK-NEXT: vchlf %v0, %v1, %v3
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; CHECK-NEXT: vlgvf %r13, %v0, 0
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; CHECK-NEXT: rosbg %r2, %r13, 56, 56, 7
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; CHECK-NEXT: vlgvf %r13, %v0, 1
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; CHECK-NEXT: rosbg %r2, %r13, 57, 57, 6
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; CHECK-NEXT: vlgvf %r13, %v0, 2
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; CHECK-NEXT: rosbg %r2, %r13, 58, 58, 5
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; CHECK-NEXT: vlgvf %r13, %v0, 3
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; CHECK-NEXT: rosbg %r2, %r13, 59, 59, 4
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; CHECK-NEXT: nilf %r4, 1
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; CHECK-NEXT: rosbg %r2, %r4, 32, 60, 3
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; CHECK-NEXT: rosbg %r2, %r3, 32, 61, 2
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; CHECK-NEXT: rosbg %r2, %r5, 32, 62, 1
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; CHECK-NEXT: or %r2, %r14
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; CHECK-NEXT: vlgvb %r4, %v0, 1
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; CHECK-NEXT: vlgvb %r3, %v0, 0
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; CHECK-NEXT: risbg %r3, %r3, 48, 176, 15
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; CHECK-NEXT: rosbg %r3, %r4, 49, 49, 14
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; CHECK-NEXT: vlgvb %r4, %v0, 2
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; CHECK-NEXT: rosbg %r3, %r4, 50, 50, 13
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; CHECK-NEXT: vlgvb %r4, %v0, 3
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; CHECK-NEXT: rosbg %r3, %r4, 51, 51, 12
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; CHECK-NEXT: vlgvb %r4, %v0, 4
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; CHECK-NEXT: rosbg %r3, %r4, 52, 52, 11
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; CHECK-NEXT: vlgvb %r4, %v0, 5
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; CHECK-NEXT: rosbg %r3, %r4, 53, 53, 10
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; CHECK-NEXT: vlgvb %r4, %v0, 6
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; CHECK-NEXT: rosbg %r3, %r4, 54, 54, 9
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; CHECK-NEXT: vlgvb %r4, %v0, 7
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; CHECK-NEXT: rosbg %r3, %r4, 55, 55, 8
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; CHECK-NEXT: vlgvb %r4, %v0, 8
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; CHECK-NEXT: rosbg %r3, %r4, 56, 56, 7
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; CHECK-NEXT: vlgvb %r4, %v0, 9
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; CHECK-NEXT: rosbg %r3, %r4, 57, 57, 6
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; CHECK-NEXT: vlgvb %r4, %v0, 10
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; CHECK-NEXT: rosbg %r3, %r4, 58, 58, 5
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; CHECK-NEXT: vlgvb %r4, %v0, 11
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; CHECK-NEXT: rosbg %r3, %r4, 59, 59, 4
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; CHECK-NEXT: vlgvb %r4, %v0, 12
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; CHECK-NEXT: rosbg %r3, %r4, 60, 60, 3
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; CHECK-NEXT: vlgvb %r4, %v0, 13
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; CHECK-NEXT: rosbg %r3, %r4, 61, 61, 2
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; CHECK-NEXT: vlgvb %r4, %v0, 14
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; CHECK-NEXT: rosbg %r3, %r4, 62, 62, 1
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; CHECK-NEXT: vlgvb %r4, %v0, 15
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; CHECK-NEXT: rosbg %r3, %r4, 63, 63, 0
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; CHECK-NEXT: xilf %r3, 4294967295
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; CHECK-NEXT: or %r3, %r2
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; CHECK-NEXT: tmll %r3, 65535
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; CHECK-NEXT: ipm %r2
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; CHECK-NEXT: afi %r2, -268435456
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; CHECK-NEXT: srl %r2, 31
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; CHECK-NEXT: nr %r2, %r1
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; CHECK-NEXT: nr %r2, %r0
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; CHECK-NEXT: larl %r1, g
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; CHECK-NEXT: stc %r2, 0(%r1)
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; CHECK-NEXT: lmg %r13, %r15, 272(%r15)
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; CHECK-NEXT: br %r14
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entry:
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%n = alloca i32, align 4
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call void @llvm.lifetime.start.p0(i64 4, ptr nonnull %n) #2
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%e.promoted9.i = load i32, ptr @e, align 4
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%bf.load.i = load i24, ptr getelementptr inbounds (%struct.anon.0.1.2.3.8.77, ptr @f, i64 0, i32 2), align 4
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%tobool.not.1.i = icmp ult i24 %bf.load.i, 128
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%bf.load.2.i = load i24, ptr getelementptr inbounds (%struct.anon.0.1.2.3.8.77, ptr @f, i64 0, i32 2), align 4
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%bf.load.2.i.fr = freeze i24 %bf.load.2.i
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%tobool.not.2.i = icmp ult i24 %bf.load.2.i.fr, 128
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%bf.load.427.i = load i24, ptr getelementptr inbounds (%struct.anon.0.1.2.3.8.77, ptr @f, i64 0, i32 2), align 4
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%bf.load.3.5.i = load i24, ptr getelementptr inbounds (%struct.anon.0.1.2.3.8.77, ptr @f, i64 0, i32 2), align 4
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%bf.load.2.6.i = load i24, ptr getelementptr inbounds (%struct.anon.0.1.2.3.8.77, ptr @f, i64 0, i32 2), align 4
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%0 = insertelement <16 x i24> poison, i24 %bf.load.2.6.i, i64 0
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%1 = insertelement <16 x i24> %0, i24 %bf.load.2.6.i, i64 1
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%2 = insertelement <16 x i24> %1, i24 %bf.load.3.5.i, i64 3
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%3 = insertelement <16 x i24> %2, i24 %bf.load.3.5.i, i64 5
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%4 = insertelement <16 x i24> %3, i24 poison, i64 7
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%5 = insertelement <16 x i24> %4, i24 poison, i64 9
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%6 = insertelement <16 x i24> %5, i24 %bf.load.427.i, i64 11
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%7 = insertelement <16 x i24> %6, i24 %bf.load.427.i, i64 13
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%8 = insertelement <16 x i24> %7, i24 %bf.load.2.i.fr, i64 15
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%9 = shufflevector <16 x i24> %8, <16 x i24> poison, <16 x i32> <i32 0, i32 1, i32 0, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7, i32 9, i32 9, i32 11, i32 11, i32 13, i32 13, i32 15>
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%.fr = freeze <16 x i24> %9
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%10 = icmp ugt <16 x i24> %.fr, <i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127, i24 127>
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%11 = bitcast <16 x i1> %10 to i16
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%12 = icmp eq i16 %11, 0
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%13 = freeze <16 x i1> poison
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%14 = bitcast <16 x i1> %13 to i16
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%15 = icmp eq i16 %14, -1
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%op.rdx = and i1 %12, %15
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%op.rdx1 = and i1 %op.rdx, %tobool.not.2.i
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%op.rdx2 = select i1 %op.rdx1, i1 %tobool.not.1.i, i1 false
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%16 = trunc i32 %e.promoted9.i to i8
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%17 = and i8 %16, 1
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%18 = select i1 false, i8 0, i8 %17
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%conv14.i = select i1 %op.rdx2, i8 %18, i8 0
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store i8 %conv14.i, ptr @g, align 2
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ret void
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}
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attributes #0 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
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attributes #1 = { nounwind "target-features"="+transactional-execution,+vector" }
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attributes #2 = { nounwind }
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