`sret` arguments are always going to reside in the stack/`alloca` address space, which makes the current formulation where their AS is derived from the pointee somewhat quaint. This patch ensures that `sret` ends up pointing to the `alloca` AS in IR function signatures, and also guards agains trying to pass a casted `alloca`d pointer to a `sret` arg, which can happen for most languages, when compiled for targets that have a non-zero `alloca` AS (e.g. AMDGCN) / map `LangAS::default` to a non-zero value (SPIR-V). A target could still choose to do something different here, by e.g. overriding `classifyReturnType` behaviour. In a broader sense, this patch extends non-aliased indirect args to also carry an AS, which leads to changing the `getIndirect()` interface. At the moment we're only using this for (indirect) returns, but it allows for future handling of indirect args themselves. We default to using the AllocaAS as that matches what Clang is currently doing, however if, in the future, a target would opt for e.g. placing indirect returns in some other storage, with another AS, this will require revisiting. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com> Co-authored-by: Matt Arsenault <Matthew.Arsenault@amd.com>
403 lines
15 KiB
C++
403 lines
15 KiB
C++
//===- NVPTX.cpp ----------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ABIInfoImpl.h"
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#include "TargetInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/IntrinsicsNVPTX.h"
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using namespace clang;
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using namespace clang::CodeGen;
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//===----------------------------------------------------------------------===//
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// NVPTX ABI Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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class NVPTXTargetCodeGenInfo;
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class NVPTXABIInfo : public ABIInfo {
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NVPTXTargetCodeGenInfo &CGInfo;
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public:
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NVPTXABIInfo(CodeGenTypes &CGT, NVPTXTargetCodeGenInfo &Info)
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: ABIInfo(CGT), CGInfo(Info) {}
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ABIArgInfo classifyReturnType(QualType RetTy) const;
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ABIArgInfo classifyArgumentType(QualType Ty) const;
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void computeInfo(CGFunctionInfo &FI) const override;
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RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
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AggValueSlot Slot) const override;
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bool isUnsupportedType(QualType T) const;
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ABIArgInfo coerceToIntArrayWithLimit(QualType Ty, unsigned MaxSize) const;
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};
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class NVPTXTargetCodeGenInfo : public TargetCodeGenInfo {
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public:
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NVPTXTargetCodeGenInfo(CodeGenTypes &CGT)
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: TargetCodeGenInfo(std::make_unique<NVPTXABIInfo>(CGT, *this)) {}
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void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV,
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CodeGen::CodeGenModule &M) const override;
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bool shouldEmitStaticExternCAliases() const override;
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llvm::Constant *getNullPointer(const CodeGen::CodeGenModule &CGM,
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llvm::PointerType *T,
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QualType QT) const override;
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llvm::Type *getCUDADeviceBuiltinSurfaceDeviceType() const override {
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// On the device side, surface reference is represented as an object handle
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// in 64-bit integer.
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return llvm::Type::getInt64Ty(getABIInfo().getVMContext());
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}
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llvm::Type *getCUDADeviceBuiltinTextureDeviceType() const override {
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// On the device side, texture reference is represented as an object handle
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// in 64-bit integer.
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return llvm::Type::getInt64Ty(getABIInfo().getVMContext());
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}
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bool emitCUDADeviceBuiltinSurfaceDeviceCopy(CodeGenFunction &CGF, LValue Dst,
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LValue Src) const override {
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emitBuiltinSurfTexDeviceCopy(CGF, Dst, Src);
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return true;
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}
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bool emitCUDADeviceBuiltinTextureDeviceCopy(CodeGenFunction &CGF, LValue Dst,
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LValue Src) const override {
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emitBuiltinSurfTexDeviceCopy(CGF, Dst, Src);
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return true;
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}
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// Adds a NamedMDNode with GV, Name, and Operand as operands, and adds the
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// resulting MDNode to the nvvm.annotations MDNode.
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static void addNVVMMetadata(llvm::GlobalValue *GV, StringRef Name,
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int Operand);
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static void
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addGridConstantNVVMMetadata(llvm::GlobalValue *GV,
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const SmallVectorImpl<int> &GridConstantArgs);
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private:
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static void emitBuiltinSurfTexDeviceCopy(CodeGenFunction &CGF, LValue Dst,
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LValue Src) {
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llvm::Value *Handle = nullptr;
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llvm::Constant *C =
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llvm::dyn_cast<llvm::Constant>(Src.getAddress().emitRawPointer(CGF));
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// Lookup `addrspacecast` through the constant pointer if any.
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if (auto *ASC = llvm::dyn_cast_or_null<llvm::AddrSpaceCastOperator>(C))
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C = llvm::cast<llvm::Constant>(ASC->getPointerOperand());
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if (auto *GV = llvm::dyn_cast_or_null<llvm::GlobalVariable>(C)) {
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// Load the handle from the specific global variable using
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// `nvvm.texsurf.handle.internal` intrinsic.
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Handle = CGF.EmitRuntimeCall(
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CGF.CGM.getIntrinsic(llvm::Intrinsic::nvvm_texsurf_handle_internal,
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{GV->getType()}),
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{GV}, "texsurf_handle");
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} else
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Handle = CGF.EmitLoadOfScalar(Src, SourceLocation());
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CGF.EmitStoreOfScalar(Handle, Dst);
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}
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};
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/// Checks if the type is unsupported directly by the current target.
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bool NVPTXABIInfo::isUnsupportedType(QualType T) const {
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ASTContext &Context = getContext();
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if (!Context.getTargetInfo().hasFloat16Type() && T->isFloat16Type())
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return true;
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if (!Context.getTargetInfo().hasFloat128Type() &&
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(T->isFloat128Type() ||
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(T->isRealFloatingType() && Context.getTypeSize(T) == 128)))
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return true;
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if (const auto *EIT = T->getAs<BitIntType>())
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return EIT->getNumBits() >
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(Context.getTargetInfo().hasInt128Type() ? 128U : 64U);
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if (!Context.getTargetInfo().hasInt128Type() && T->isIntegerType() &&
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Context.getTypeSize(T) > 64U)
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return true;
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if (const auto *AT = T->getAsArrayTypeUnsafe())
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return isUnsupportedType(AT->getElementType());
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const auto *RT = T->getAs<RecordType>();
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if (!RT)
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return false;
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const RecordDecl *RD = RT->getDecl();
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// If this is a C++ record, check the bases first.
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if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD))
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for (const CXXBaseSpecifier &I : CXXRD->bases())
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if (isUnsupportedType(I.getType()))
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return true;
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for (const FieldDecl *I : RD->fields())
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if (isUnsupportedType(I->getType()))
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return true;
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return false;
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}
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/// Coerce the given type into an array with maximum allowed size of elements.
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ABIArgInfo NVPTXABIInfo::coerceToIntArrayWithLimit(QualType Ty,
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unsigned MaxSize) const {
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// Alignment and Size are measured in bits.
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const uint64_t Size = getContext().getTypeSize(Ty);
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const uint64_t Alignment = getContext().getTypeAlign(Ty);
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const unsigned Div = std::min<unsigned>(MaxSize, Alignment);
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llvm::Type *IntType = llvm::Type::getIntNTy(getVMContext(), Div);
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const uint64_t NumElements = (Size + Div - 1) / Div;
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return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements));
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}
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ABIArgInfo NVPTXABIInfo::classifyReturnType(QualType RetTy) const {
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if (RetTy->isVoidType())
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return ABIArgInfo::getIgnore();
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if (getContext().getLangOpts().OpenMP &&
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getContext().getLangOpts().OpenMPIsTargetDevice &&
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isUnsupportedType(RetTy))
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return coerceToIntArrayWithLimit(RetTy, 64);
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// note: this is different from default ABI
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if (!RetTy->isScalarType())
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return ABIArgInfo::getDirect();
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// Treat an enum type as its underlying type.
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if (const EnumType *EnumTy = RetTy->getAs<EnumType>())
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RetTy = EnumTy->getDecl()->getIntegerType();
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return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy)
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: ABIArgInfo::getDirect());
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}
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ABIArgInfo NVPTXABIInfo::classifyArgumentType(QualType Ty) const {
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// Treat an enum type as its underlying type.
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if (const EnumType *EnumTy = Ty->getAs<EnumType>())
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Ty = EnumTy->getDecl()->getIntegerType();
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// Return aggregates type as indirect by value
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if (isAggregateTypeForABI(Ty)) {
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// Under CUDA device compilation, tex/surf builtin types are replaced with
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// object types and passed directly.
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if (getContext().getLangOpts().CUDAIsDevice) {
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if (Ty->isCUDADeviceBuiltinSurfaceType())
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return ABIArgInfo::getDirect(
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CGInfo.getCUDADeviceBuiltinSurfaceDeviceType());
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if (Ty->isCUDADeviceBuiltinTextureType())
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return ABIArgInfo::getDirect(
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CGInfo.getCUDADeviceBuiltinTextureDeviceType());
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}
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return getNaturalAlignIndirect(
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Ty, /* AddrSpace */ getDataLayout().getAllocaAddrSpace(),
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/* byval */ true);
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}
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if (const auto *EIT = Ty->getAs<BitIntType>()) {
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if ((EIT->getNumBits() > 128) ||
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(!getContext().getTargetInfo().hasInt128Type() &&
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EIT->getNumBits() > 64))
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return getNaturalAlignIndirect(
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Ty, /* AddrSpace */ getDataLayout().getAllocaAddrSpace(),
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/* byval */ true);
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}
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return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty)
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: ABIArgInfo::getDirect());
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}
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void NVPTXABIInfo::computeInfo(CGFunctionInfo &FI) const {
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if (!getCXXABI().classifyReturnType(FI))
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FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
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for (auto &&[ArgumentsCount, I] : llvm::enumerate(FI.arguments()))
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I.info = ArgumentsCount < FI.getNumRequiredArgs()
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? classifyArgumentType(I.type)
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: ABIArgInfo::getDirect();
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// Always honor user-specified calling convention.
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if (FI.getCallingConvention() != llvm::CallingConv::C)
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return;
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FI.setEffectiveCallingConvention(getRuntimeCC());
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}
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RValue NVPTXABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
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QualType Ty, AggValueSlot Slot) const {
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return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*IsIndirect=*/false,
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getContext().getTypeInfoInChars(Ty),
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CharUnits::fromQuantity(1),
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/*AllowHigherAlign=*/true, Slot);
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}
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void NVPTXTargetCodeGenInfo::setTargetAttributes(
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const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &M) const {
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if (GV->isDeclaration())
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return;
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const VarDecl *VD = dyn_cast_or_null<VarDecl>(D);
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if (VD) {
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if (M.getLangOpts().CUDA) {
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if (VD->getType()->isCUDADeviceBuiltinSurfaceType())
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addNVVMMetadata(GV, "surface", 1);
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else if (VD->getType()->isCUDADeviceBuiltinTextureType())
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addNVVMMetadata(GV, "texture", 1);
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return;
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}
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}
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const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D);
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if (!FD)
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return;
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llvm::Function *F = cast<llvm::Function>(GV);
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// Perform special handling in OpenCL mode
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if (M.getLangOpts().OpenCL) {
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// Use OpenCL function attributes to check for kernel functions
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// By default, all functions are device functions
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if (FD->hasAttr<OpenCLKernelAttr>()) {
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// OpenCL __kernel functions get kernel metadata
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// Create !{<func-ref>, metadata !"kernel", i32 1} node
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F->setCallingConv(llvm::CallingConv::PTX_Kernel);
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// And kernel functions are not subject to inlining
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F->addFnAttr(llvm::Attribute::NoInline);
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}
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}
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// Perform special handling in CUDA mode.
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if (M.getLangOpts().CUDA) {
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// CUDA __global__ functions get a kernel metadata entry. Since
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// __global__ functions cannot be called from the device, we do not
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// need to set the noinline attribute.
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if (FD->hasAttr<CUDAGlobalAttr>()) {
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SmallVector<int, 10> GCI;
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for (auto IV : llvm::enumerate(FD->parameters()))
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if (IV.value()->hasAttr<CUDAGridConstantAttr>())
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// For some reason arg indices are 1-based in NVVM
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GCI.push_back(IV.index() + 1);
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// Create !{<func-ref>, metadata !"kernel", i32 1} node
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F->setCallingConv(llvm::CallingConv::PTX_Kernel);
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addGridConstantNVVMMetadata(F, GCI);
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}
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if (CUDALaunchBoundsAttr *Attr = FD->getAttr<CUDALaunchBoundsAttr>())
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M.handleCUDALaunchBoundsAttr(F, Attr);
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}
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// Attach kernel metadata directly if compiling for NVPTX.
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if (FD->hasAttr<NVPTXKernelAttr>()) {
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F->setCallingConv(llvm::CallingConv::PTX_Kernel);
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}
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}
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void NVPTXTargetCodeGenInfo::addNVVMMetadata(llvm::GlobalValue *GV,
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StringRef Name, int Operand) {
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llvm::Module *M = GV->getParent();
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llvm::LLVMContext &Ctx = M->getContext();
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// Get "nvvm.annotations" metadata node
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llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
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SmallVector<llvm::Metadata *, 5> MDVals = {
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llvm::ConstantAsMetadata::get(GV), llvm::MDString::get(Ctx, Name),
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llvm::ConstantAsMetadata::get(
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llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), Operand))};
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// Append metadata to nvvm.annotations
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MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
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}
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void NVPTXTargetCodeGenInfo::addGridConstantNVVMMetadata(
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llvm::GlobalValue *GV, const SmallVectorImpl<int> &GridConstantArgs) {
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llvm::Module *M = GV->getParent();
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llvm::LLVMContext &Ctx = M->getContext();
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// Get "nvvm.annotations" metadata node
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llvm::NamedMDNode *MD = M->getOrInsertNamedMetadata("nvvm.annotations");
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SmallVector<llvm::Metadata *, 5> MDVals = {llvm::ConstantAsMetadata::get(GV)};
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if (!GridConstantArgs.empty()) {
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SmallVector<llvm::Metadata *, 10> GCM;
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for (int I : GridConstantArgs)
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GCM.push_back(llvm::ConstantAsMetadata::get(
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llvm::ConstantInt::get(llvm::Type::getInt32Ty(Ctx), I)));
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MDVals.append({llvm::MDString::get(Ctx, "grid_constant"),
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llvm::MDNode::get(Ctx, GCM)});
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}
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// Append metadata to nvvm.annotations
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MD->addOperand(llvm::MDNode::get(Ctx, MDVals));
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}
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bool NVPTXTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {
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return false;
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}
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llvm::Constant *
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NVPTXTargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM,
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llvm::PointerType *PT,
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QualType QT) const {
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auto &Ctx = CGM.getContext();
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if (PT->getAddressSpace() != Ctx.getTargetAddressSpace(LangAS::opencl_local))
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return llvm::ConstantPointerNull::get(PT);
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auto NPT = llvm::PointerType::get(
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PT->getContext(), Ctx.getTargetAddressSpace(LangAS::opencl_generic));
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return llvm::ConstantExpr::getAddrSpaceCast(
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llvm::ConstantPointerNull::get(NPT), PT);
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}
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} // namespace
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void CodeGenModule::handleCUDALaunchBoundsAttr(llvm::Function *F,
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const CUDALaunchBoundsAttr *Attr,
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int32_t *MaxThreadsVal,
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int32_t *MinBlocksVal,
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int32_t *MaxClusterRankVal) {
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// Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
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llvm::APSInt MaxThreads(32);
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MaxThreads = Attr->getMaxThreads()->EvaluateKnownConstInt(getContext());
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if (MaxThreads > 0) {
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if (MaxThreadsVal)
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*MaxThreadsVal = MaxThreads.getExtValue();
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if (F) {
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// Create !{<func-ref>, metadata !"maxntidx", i32 <val>} node
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NVPTXTargetCodeGenInfo::addNVVMMetadata(F, "maxntidx",
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MaxThreads.getExtValue());
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}
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}
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// min and max blocks is an optional argument for CUDALaunchBoundsAttr. If it
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// was not specified in __launch_bounds__ or if the user specified a 0 value,
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// we don't have to add a PTX directive.
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if (Attr->getMinBlocks()) {
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llvm::APSInt MinBlocks(32);
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MinBlocks = Attr->getMinBlocks()->EvaluateKnownConstInt(getContext());
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if (MinBlocks > 0) {
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if (MinBlocksVal)
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*MinBlocksVal = MinBlocks.getExtValue();
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if (F)
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F->addFnAttr("nvvm.minctasm", llvm::utostr(MinBlocks.getExtValue()));
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}
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}
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if (Attr->getMaxBlocks()) {
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llvm::APSInt MaxBlocks(32);
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MaxBlocks = Attr->getMaxBlocks()->EvaluateKnownConstInt(getContext());
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if (MaxBlocks > 0) {
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if (MaxClusterRankVal)
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*MaxClusterRankVal = MaxBlocks.getExtValue();
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if (F)
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F->addFnAttr("nvvm.maxclusterrank",
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llvm::utostr(MaxBlocks.getExtValue()));
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}
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}
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}
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std::unique_ptr<TargetCodeGenInfo>
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CodeGen::createNVPTXTargetCodeGenInfo(CodeGenModule &CGM) {
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return std::make_unique<NVPTXTargetCodeGenInfo>(CGM.getTypes());
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}
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