Matt Arsenault 3b36bb1d87 AMDGPU: Enable ConstrainCopy DAG mutation ...

This fixes a probably unintended divergence from the default
scheduler behavior.

llvm-svn: 287146

2016-11-16 20:35:23 +00:00

..

AArch64

[AArch64] Handle vector types in replaceZeroVectorStore.

2016-11-16 19:35:19 +00:00

AMDGPU

AMDGPU: Enable ConstrainCopy DAG mutation

2016-11-16 20:35:23 +00:00

ARM

[ARM] Add machine scheduler for Cortex-R52

2016-11-15 11:34:54 +00:00

AVR

[AVR] Add a selection of CodeGen tests

2016-11-09 23:46:52 +00:00

BPF

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Generic

Add -O0 support for @llvm.invariant.group.barrier by discarding it if it gets to ISel.

2016-11-07 16:47:20 +00:00

Hexagon

[Hexagon] Remove unsafe load instructions that affect Stack Slot Coloring

2016-11-14 17:11:00 +00:00

Inputs

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Lanai

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Mips

[mips] Fix unsigned/signed type error

2016-11-16 11:29:07 +00:00

MIR

MIRParser: Add support for parsing vreg reg alloc hints

2016-11-15 00:03:14 +00:00

MSP430

Fix PR27500: on MSP430 the branch destination offset is measured in words, not bytes.

2016-11-08 17:19:59 +00:00

NVPTX

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PowerPC

Always use relative jump table encodings on PowerPC64.

2016-11-16 00:37:30 +00:00

SPARC

ScheduleDAGInstrs: Add condjump deps to addSchedBarrierDeps()

2016-11-11 01:34:21 +00:00

SystemZ

[SystemZ] Support CL(G)T instructions

2016-11-11 12:48:26 +00:00

Thumb

Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"

2016-11-03 14:08:01 +00:00

Thumb2

Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"

2016-11-03 14:08:01 +00:00

WebAssembly

[WebAssembly] Convert stackified IMPLICIT_DEF into constant 0.

2016-11-08 19:40:38 +00:00

WinEH

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X86

[x86] add fake scalar FP logic instructions to ReplaceableInstrs to save some bytes

2016-11-16 17:42:40 +00:00

XCore

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