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clang-p2996/llvm/lib/Target/RISCV
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Fangrui Song fe56c4c019 [MC] Remove unneeded VK_None argument from MCSymbolRefExpr::create. NFC
2025-03-05 23:14:04 -08:00
..
AsmParser
[MC] Remove unneeded VK_None argument from MCSymbolRefExpr::create. NFC
2025-03-05 23:14:04 -08:00
Disassembler
[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)
2025-03-06 12:01:53 +05:30
GISel
[RISCV] Check subtarget feature in getBrCond (#129859)
2025-03-05 19:38:40 +05:30
MCA
Prune a redundant include "RISCVISelDAGToDAG.h" (fixup for #128978)
2025-03-01 14:04:48 +09:00
MCTargetDesc
[MC] Remove unneeded VK_None argument from MCSymbolRefExpr::create. NFC
2025-03-05 23:14:04 -08:00
TargetInfo
…
CMakeLists.txt
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
RISCV.h
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
RISCV.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVAsmPrinter.cpp
[MC] Remove unneeded VK_None argument from MCSymbolRefExpr::create. NFC
2025-03-05 23:14:04 -08:00
RISCVCallingConv.cpp
…
RISCVCallingConv.h
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RISCVCallingConv.td
[RISCV] Implement getIPRACSRegs hook (#125586)
2025-02-04 10:02:42 -03:00
RISCVCodeGenPrepare.cpp
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RISCVCombine.td
[GISel] Combine (neg (min/max x, (neg x))) into (max/min x, (neg x)) (#120998)
2025-01-02 16:29:34 -08:00
RISCVConstantPoolValue.cpp
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RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)
2024-12-06 15:16:07 +05:30
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Support multiple memory operands in expandRV32ZdinxStore.
2025-01-27 22:10:51 -08:00
RISCVFeatures.td
[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)
2025-03-06 12:01:53 +05:30
RISCVFoldMemOffset.cpp
Recommit "[RISCV] Add a pass to remove ADDI by reassociating to fold into load/store address. (#127151)"
2025-02-19 12:11:00 -08:00
RISCVFrameLowering.cpp
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVFrameLowering.h
[RISCV] Stack clash protection for dynamic alloca (#122508)
2025-01-16 11:58:42 -08:00
RISCVGatherScatterLowering.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVGISel.td
[RISCV] Move GIComplexOperandMatcher and GICustomOperandRenderer next to their SelectionDAG equivalents. NFC (#119729)
2024-12-12 14:41:57 -08:00
RISCVIndirectBranchTracking.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVInstrFormats.td
[RISCV] Remove Inst bits from Pseudo tablegen class. NFC
2025-02-23 15:08:55 -08:00
RISCVInstrFormatsC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrFormatsV.td
[RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104)
2025-02-27 13:14:22 -08:00
RISCVInstrGISel.td
…
RISCVInstrInfo.cpp
[RISCV] Check subtarget feature in getBrCond (#129859)
2025-03-05 19:38:40 +05:30
RISCVInstrInfo.h
[RISCV] Check subtarget feature in getBrCond (#129859)
2025-03-05 19:38:40 +05:30
RISCVInstrInfo.td
[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)
2025-02-26 20:03:02 -08:00
RISCVInstrInfoA.td
[RISCV] Remove unnecessary patterns from RISCVInstrInfoA.td. NFC
2024-12-17 10:24:50 -08:00
RISCVInstrInfoC.td
[RISCV] Add a default assignment of Inst{12-7} to RVInst16CSS. NFC
2025-01-10 14:28:54 -08:00
RISCVInstrInfoD.td
[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)
2025-02-27 14:56:54 -08:00
RISCVInstrInfoF.td
[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)
2025-02-27 14:56:54 -08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoSFB.td
…
RISCVInstrInfoV.td
[RISCV][MCA] Pick the correct VPseudo sched class for indexed memory operation (#128978)
2025-02-28 16:34:50 -08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove unnecessary entries from RISCVVInversePseudosTable. NFC (#128376)
2025-02-24 09:31:55 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Select mask operands as virtual registers and eliminate uses of vmv0 (#125026)
2025-02-12 12:06:55 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add policy operand to masked vector compare pseudos. Remove ForceTailAgnostic. NFC (#127575)
2025-02-18 07:05:05 -08:00
RISCVInstrInfoXCV.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoXMips.td
[RISCV] Simplify MIPS CCMov patterns. NFC (#125318)
2025-02-01 09:36:31 -08:00
RISCVInstrInfoXqccmp.td
[RISCV] Add Xqccmp 0.1 Assembly Support (#128731)
2025-02-26 20:03:02 -08:00
RISCVInstrInfoXqci.td
[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)
2025-03-06 12:01:53 +05:30
RISCVInstrInfoXRivos.td
[RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104)
2025-02-27 13:14:22 -08:00
RISCVInstrInfoXSf.td
[RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)
2025-02-27 19:25:14 -08:00
RISCVInstrInfoXTHead.td
[RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC
2024-12-29 12:44:33 -08:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
[RISCV][NFCI] Rationalize Immediate Definitions (#120718)
2024-12-21 09:47:07 +00:00
RISCVInstrInfoZa.td
[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)
2025-02-27 14:56:54 -08:00
RISCVInstrInfoZalasr.td
[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)
2024-12-17 00:19:45 -08:00
RISCVInstrInfoZb.td
[RISCV] Support Zb*/P Shared Instructions (#127160)
2025-02-15 22:26:02 +08:00
RISCVInstrInfoZc.td
[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)
2025-02-27 14:56:54 -08:00
RISCVInstrInfoZcmop.td
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RISCVInstrInfoZfa.td
[RISCV][NFC] Adopt DiagnosticString interface (#126290)
2025-02-08 07:59:55 -08:00
RISCVInstrInfoZfbfmin.td
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RISCVInstrInfoZfh.td
[RISCV] Consolidate some DecoderNamespaces for standard extensions. (#128954)
2025-02-27 14:56:54 -08:00
RISCVInstrInfoZicbo.td
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RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
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RISCVInstrInfoZimop.td
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RISCVInstrInfoZk.td
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RISCVInstrInfoZvfbf.td
[RISCV] Add VL and VTYPE to implicit uses on MC vector instructions that also use FRM (#129130)
2025-02-27 19:25:14 -08:00
RISCVInstrInfoZvk.td
[RISCV] Order the implicit defs/uses of vl/vtype on MC instructions the same as the pseudo version. (#129104)
2025-02-27 13:14:22 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (#129172)
2025-02-27 19:30:31 -08:00
RISCVISelDAGToDAG.h
[RISCV] Move RISCV vector load/store searchable tables from RISCVISelDAGToDAG.cpp to RISCVBaseInfo.cpp. NFC (#129172)
2025-02-27 19:30:31 -08:00
RISCVISelLowering.cpp
[RISCV] Collect shuffle mask for the lane not by createSequentialMask (#129830)
2025-03-05 15:31:16 +08:00
RISCVISelLowering.h
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVLandingPadSetup.cpp
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RISCVMachineFunctionInfo.cpp
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVMachineFunctionInfo.h
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVMergeBaseOffset.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVMoveMerger.cpp
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVOptWInstrs.cpp
[RISCV] Add PseudoCCMOVGPRNoX0 to RISCVOptWInstrs.
2025-01-31 15:09:11 -08:00
RISCVPfmCounters.td
[RISCV][llvm-exegesis] Add default Pfm cycle counter. (#121866)
2025-01-07 09:51:34 -08:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV] Correct the pass name for RISCVPostRAExpandPseudo.
2024-12-05 16:43:30 -08:00
RISCVProcessors.td
[RISCV] Tune flag for fast vrgather.vv (#124664)
2025-03-03 16:04:49 -08:00
RISCVProfiles.td
…
RISCVPushPopOptimizer.cpp
[RISCV] Xqccmp Code Generation (#128815)
2025-03-05 10:59:45 -08:00
RISCVRedundantCopyElimination.cpp
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RISCVRegisterInfo.cpp
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVRegisterInfo.h
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVRegisterInfo.td
[RISCV] Improve Errors for GPRNoX0 Reg Class (#126397)
2025-02-10 17:21:51 -08:00
RISCVSchedGenericOOO.td
[RISCV] Add a generic OOO CPU (#120712)
2025-02-14 17:35:02 +08:00
RISCVSchedMIPSP8700.td
[RISCV] Remove duplicate WriteRes<WriteJalr for MIPSP8700. (#123865)
2025-01-22 10:37:01 -08:00
RISCVSchedRocket.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSiFive7.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVSchedSiFiveP400.td
[RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (#128786)
2025-02-26 09:05:51 -08:00
RISCVSchedSiFiveP500.td
[RISCV] Add P550 scheduler model. (#124639)
2025-01-27 22:40:05 -08:00
RISCVSchedSiFiveP600.td
[RISCV] Update MicroOpBufferSize in P400 & P600 scheduling models (#128786)
2025-02-26 09:05:51 -08:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Remove some unnecessary UnsupportedSched* that are implied by others. NFC
2025-01-21 18:00:52 -08:00
RISCVSchedSyntacoreSCR7.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedSyntacoreSCR345.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSchedTTAscalonD8.td
[RISC-V] Base scheduling model for tt-ascalon-d8 (#120160)
2024-12-20 15:30:17 -05:00
RISCVSchedule.td
[RISCV] Add missing ReadFMA16Addend in UnsupportedSchedZfh
2024-12-31 17:22:08 +08:00
RISCVScheduleV.td
[RISCV] Fix typos discovered by codespell (NFC) (#126191)
2025-02-07 13:35:30 +05:30
RISCVScheduleXSf.td
…
RISCVScheduleZb.td
…
RISCVScheduleZvk.td
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RISCVSchedXiangShanNanHu.td
[RISCV] Use inheritance to simplify usage of the UnsupportedSched* multiclasses. NFC (#120329)
2024-12-17 21:32:50 -08:00
RISCVSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
RISCVSubtarget.cpp
[RISCV] Add MIPS extensions (#121394)
2025-01-28 08:04:09 +01:00
RISCVSubtarget.h
[RISCV] Tune flag for fast vrgather.vv (#124664)
2025-03-03 16:04:49 -08:00
RISCVSystemOperands.td
[RISCV] Support [mh]edelegh CSRs (#121634)
2025-02-16 13:41:46 -08:00
RISCVTargetMachine.cpp
[RISCV] Move VMV0 elimination past machine SSA opts (#126850)
2025-02-20 12:41:05 +08:00
RISCVTargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Simplify costShuffleViaVRegSplitting [nfc] (#129766)
2025-03-04 13:35:52 -08:00
RISCVTargetTransformInfo.h
[RISCV] Enable scalable loop vectorization for fmax/fmin reductions with f16/bf16 type for zvfhmin/zvfbfmin (#129629)
2025-03-04 16:49:24 +08:00
RISCVVectorMaskDAGMutation.cpp
[RISCV] Adjust RISCVVectorMaskDAGMutation to look for copy to V0 (#129296)
2025-03-05 08:56:09 -08:00
RISCVVectorPeephole.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Move mayReadPastVL check into getMinimumVLForUser. NFC (#127972)
2025-02-20 20:17:18 +08:00
RISCVVMV0Elimination.cpp
[RISCV] Delete dead COPYs to vmv0 during vmv0 elimination
2025-02-26 23:09:50 +08:00
RISCVZacasABIFix.cpp
…