8424bf207e
This patch adds support for the next-generation arch15 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Detection of arch15 as host processor. - Assembler/disassembler support for new instructions. - Exploitation of new instructions for code generation. - New vector (signed|unsigned|bool) __int128 data types. - New LLVM intrinsics for certain new instructions. - Support for low-level builtins mapped to new LLVM intrinsics. - New high-level intrinsics in vecintrin.h. - Indicate support by defining __VEC__ == 10305. Note: No currently available Z system supports the arch15 architecture. Once new systems become available, the official system name will be added as supported -march name.
45 lines
2.0 KiB
TableGen
45 lines
2.0 KiB
TableGen
//===-- SystemZ.td - SystemZ processors and features ---------*- tblgen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Processor definitions.
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//
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// For compatibility with other compilers on the platform, each model can
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// be identified either by the system name (e.g. z10) or the level of the
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// architecture the model supports, as identified by the edition level
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// of the z/Architecture Principles of Operation document (e.g. arch8).
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//
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// The minimum architecture level supported by LLVM is as defined in
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// the Eighth Edition of the PoP (i.e. as implemented on z10).
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//
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic", NoSchedModel, []>;
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def : ProcessorModel<"arch8", NoSchedModel, Arch8SupportedFeatures.List>;
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def : ProcessorModel<"z10", NoSchedModel, Arch8SupportedFeatures.List>;
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def : ProcessorModel<"arch9", Z196Model, Arch9SupportedFeatures.List>;
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def : ProcessorModel<"z196", Z196Model, Arch9SupportedFeatures.List>;
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def : ProcessorModel<"arch10", ZEC12Model, Arch10SupportedFeatures.List>;
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def : ProcessorModel<"zEC12", ZEC12Model, Arch10SupportedFeatures.List>;
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def : ProcessorModel<"arch11", Z13Model, Arch11SupportedFeatures.List>;
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def : ProcessorModel<"z13", Z13Model, Arch11SupportedFeatures.List>;
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def : ProcessorModel<"arch12", Z14Model, Arch12SupportedFeatures.List>;
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def : ProcessorModel<"z14", Z14Model, Arch12SupportedFeatures.List>;
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def : ProcessorModel<"arch13", Z15Model, Arch13SupportedFeatures.List>;
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def : ProcessorModel<"z15", Z15Model, Arch13SupportedFeatures.List>;
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def : ProcessorModel<"arch14", Z16Model, Arch14SupportedFeatures.List>;
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def : ProcessorModel<"z16", Z16Model, Arch14SupportedFeatures.List>;
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def : ProcessorModel<"arch15", Z16Model, Arch15SupportedFeatures.List>;
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