Simon Pilgrim 8eeeddb5ed [X86] lowerV8I16GeneralSingleInputShuffle - for splat PSHUFW+PSHUFD patterns, widen the splats to encourage combines (#129854) ...

For vXi16 patterns that lower to splats, ensure that PSHUFW mask splats to the entire LW/HW i64 half and then create a wide PSHUFD mask that splats the whole i64 element - this encourages further combines without depending on any unused elements from undef shuffle mask elements.

Fixes #129276

2025-03-06 14:25:57 +00:00

..

AArch64

[NFC][LLVM] Refactor llvm/test/CodeGen/AArch64/sve{2}-fcopysign.ll

2025-03-06 12:53:40 +00:00

AMDGPU

AMDGPU: Replace amdgpu-no-agpr with amdgpu-agpr-alloc (#129893)

2025-03-06 09:17:51 +07:00

ARC

…

ARM

SplitKit: Take register class directly from instruction definition (#129727)

2025-03-06 20:06:35 +07:00

AVR

…

BPF

[BPF] Add load-acquire and store-release instructions under -mcpu=v4 (#108636)

2025-03-04 09:19:39 -08:00

CSKY

[CSKY] Update fp16-promote.ll test (NFC)

2025-03-05 12:42:32 +01:00

DirectX

[HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (#127137)

2025-03-05 17:04:10 -08:00

Generic

…

Hexagon

[CodeGen][NewPM] Port MachineSink to NPM (#115434)

2025-03-03 15:49:37 +05:30

Inputs

…

Lanai

…

LoongArch

[LoongArch] Relax the restrictions of inlineasm operand modifier 'u' and 'w' (#129864)

2025-03-06 16:17:12 +08:00

M68k

…

Mips

…

MIR

[win] Enable test/CodeGen/MIR/AArch64 on Windows (#122832)

2025-03-03 09:54:28 -08:00

MLRegAlloc

…

MSP430

…

NVPTX

[NVPTX] Add Intrinsics for discard.* (#128404)

2025-03-03 22:53:49 +05:30

PowerPC

[PowerPC] hoist xxspltib out of loop body (#127121)

2025-03-03 11:14:02 -05:00

RISCV

[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)

2025-03-06 12:01:53 +05:30

SPARC

…

SPIRV

[HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (#127137)

2025-03-05 17:04:10 -08:00

SystemZ

[CodeGen][NPM] Port ExpandPostRAPseudos to NPM (#129509)

2025-03-04 11:49:09 +05:30

Thumb

[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)

2025-03-03 11:06:15 +05:30

Thumb2

…

VE

…

WebAssembly

…

WinCFGuard

…

WinEH

…

X86

[X86] lowerV8I16GeneralSingleInputShuffle - for splat PSHUFW+PSHUFD patterns, widen the splats to encourage combines (#129854)

2025-03-06 14:25:57 +00:00

XCore

…

Xtensa

…