e5f5517f91
Create a IR BB directly for the middle.block, instead of creating the IR BB during skeleton creation and then replacing the middle VPBB with a VPIRBB. This moves another part of skeleton creation to VPlan and simplififes the code slightly by removing code to disconnect the middle block and vector preheader + the corresponding DT update. NFC modulo IR block naming and block creation order, which changes the IR names for the blocks.
114 lines
5.7 KiB
LLVM
114 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -passes='loop(loop-deletion),loop-vectorize' -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s
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; Note: loop-deletion is needed to populate SCEV block dispositions.
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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define void @test_pr63368(i1 %c, ptr %A) {
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; CHECK-LABEL: define void @test_pr63368
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; CHECK-SAME: (i1 [[C:%.*]], ptr [[A:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[A]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP1]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: br i1 true, label [[EXIT_1:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 100, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: br label [[LOOP_1_HEADER:%.*]]
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; CHECK: loop.1.header:
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; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP_1_LATCH:%.*]] ]
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; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[A]], align 4
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; CHECK-NEXT: br i1 [[C]], label [[LOOP_1_LATCH]], label [[LOOP_1_LATCH]]
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; CHECK: loop.1.latch:
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; CHECK-NEXT: [[L_LCSSA:%.*]] = phi i32 [ [[L]], [[LOOP_1_HEADER]] ], [ [[L]], [[LOOP_1_HEADER]] ]
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; CHECK-NEXT: [[IV_1_NEXT]] = add nuw nsw i32 [[IV_1]], 1
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; CHECK-NEXT: [[EC_1:%.*]] = icmp eq i32 [[IV_1_NEXT]], 100
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; CHECK-NEXT: br i1 [[EC_1]], label [[EXIT_1]], label [[LOOP_1_HEADER]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: exit.1:
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; CHECK-NEXT: [[L_LCSSA_LCSSA:%.*]] = phi i32 [ [[L_LCSSA]], [[LOOP_1_LATCH]] ], [ [[TMP0]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: [[SMAX1:%.*]] = call i32 @llvm.smax.i32(i32 [[L_LCSSA_LCSSA]], i32 -1)
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[SMAX1]], 2
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP2]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH2:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
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; CHECK: vector.scevcheck:
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; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[L_LCSSA_LCSSA]], i32 -1)
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; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[SMAX]], 1
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[TMP3]] to i8
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; CHECK-NEXT: [[TMP5:%.*]] = add i8 1, [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = icmp slt i8 [[TMP5]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP3]], 255
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; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP6]], [[TMP7]]
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; CHECK-NEXT: br i1 [[TMP8]], label [[SCALAR_PH2]], label [[VECTOR_PH3:%.*]]
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; CHECK: vector.ph3:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[TMP2]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[TMP2]], [[N_MOD_VF]]
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; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[N_VEC]] to i8
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; CHECK-NEXT: br label [[VECTOR_BODY4:%.*]]
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; CHECK: vector.body4:
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; CHECK-NEXT: [[INDEX5:%.*]] = phi i32 [ 0, [[VECTOR_PH3]] ], [ [[INDEX_NEXT6:%.*]], [[VECTOR_BODY4]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = trunc i32 [[INDEX5]] to i8
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; CHECK-NEXT: [[TMP10:%.*]] = add i8 [[OFFSET_IDX]], 0
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; CHECK-NEXT: [[TMP11:%.*]] = add i8 [[TMP10]], 1
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[A]], i8 [[TMP11]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP12]], i32 0
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; CHECK-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP13]], align 1
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; CHECK-NEXT: [[INDEX_NEXT6]] = add nuw i32 [[INDEX5]], 4
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; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[INDEX_NEXT6]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK7:%.*]], label [[VECTOR_BODY4]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: middle.block7:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[TMP2]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT_2:%.*]], label [[SCALAR_PH2]]
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; CHECK: scalar.ph2:
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; CHECK-NEXT: [[BC_RESUME_VAL8:%.*]] = phi i8 [ [[TMP9]], [[MIDDLE_BLOCK7]] ], [ 0, [[EXIT_1]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
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; CHECK-NEXT: br label [[LOOP_2:%.*]]
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; CHECK: loop.2:
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; CHECK-NEXT: [[IV_2:%.*]] = phi i8 [ [[BC_RESUME_VAL8]], [[SCALAR_PH2]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_2]] ]
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; CHECK-NEXT: [[IV_2_NEXT]] = add i8 [[IV_2]], 1
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; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr i8, ptr [[A]], i8 [[IV_2_NEXT]]
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; CHECK-NEXT: store i8 0, ptr [[GEP_A]], align 1
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; CHECK-NEXT: [[IV_2_SEXT:%.*]] = sext i8 [[IV_2]] to i32
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; CHECK-NEXT: [[EC_2:%.*]] = icmp sge i32 [[L_LCSSA_LCSSA]], [[IV_2_SEXT]]
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; CHECK-NEXT: br i1 [[EC_2]], label [[LOOP_2]], label [[EXIT_2]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: exit.2:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop.1.header
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loop.1.header:
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%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1.latch ]
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%l = load i32, ptr %A
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br i1 %c, label %loop.1.latch, label %loop.1.latch
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loop.1.latch:
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%l.lcssa = phi i32 [ %l, %loop.1.header ], [ %l, %loop.1.header ]
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%iv.1.next = add nuw nsw i32 %iv.1, 1
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%ec.1 = icmp eq i32 %iv.1.next, 100
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br i1 %ec.1, label %exit.1, label %loop.1.header
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exit.1:
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%l.lcssa.lcssa = phi i32 [ %l.lcssa, %loop.1.latch ]
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br label %loop.2
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loop.2:
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%iv.2 = phi i8 [ 0, %exit.1 ], [ %iv.2.next, %loop.2 ]
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%iv.2.next = add i8 %iv.2, 1
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%gep.A = getelementptr i8, ptr %A, i8 %iv.2.next
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store i8 0, ptr %gep.A
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%iv.2.sext = sext i8 %iv.2 to i32
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%ec.2 = icmp sge i32 %l.lcssa.lcssa, %iv.2.sext
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br i1 %ec.2, label %loop.2, label %exit.2
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exit.2:
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ret void
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}
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