ee13638362
Since e39f6c1844 opt will infer the
correct datalayout when given a triple. Avoid explicitly specifying it
in tests that depend on the AMDGPU target being present to avoid the
string becoming out of sync with the TargetInfo value.
Only tests with REQUIRES: amdgpu-registered-target or a local lit.cfg
were updated to ensure that tests for non-target-specific passes that
happen to use the AMDGPU layout still pass when building with a limited
set of targets.
Reviewed By: shiltian, arsenm
Pull Request: https://github.com/llvm/llvm-project/pull/137921
60 lines
1.8 KiB
LLVM
60 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2
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; RUN: opt -passes=indvars -S < %s | FileCheck %s
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target triple = "amdgcn--amdpal"
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define void @f(ptr addrspace(7) %arg) {
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; CHECK-LABEL: define void @f
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; CHECK-SAME: (ptr addrspace(7) [[ARG:%.*]]) {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: br i1 false, label [[BB2:%.*]], label [[BB1]]
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; CHECK: bb2:
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(7) [[ARG]], i32 8
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[I4:%.*]] = load i32, ptr addrspace(7) [[SCEVGEP]], align 4
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; CHECK-NEXT: br label [[BB3]]
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;
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bb:
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br label %bb1
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bb1:
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%i = getelementptr i32, ptr addrspace(7) %arg, i32 2
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br i1 false, label %bb2, label %bb1
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bb2:
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br label %bb3
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bb3:
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%i4 = load i32, ptr addrspace(7) %i, align 4
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br label %bb3
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}
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define void @f2(<2 x ptr addrspace(7)> %arg) {
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; CHECK-LABEL: define void @f2
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; CHECK-SAME: (<2 x ptr addrspace(7)> [[ARG:%.*]]) {
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; CHECK-NEXT: bb:
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; CHECK-NEXT: br label [[BB1:%.*]]
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; CHECK: bb1:
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; CHECK-NEXT: [[P:%.*]] = extractelement <2 x ptr addrspace(7)> [[ARG]], i32 0
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; CHECK-NEXT: [[I:%.*]] = getelementptr i32, ptr addrspace(7) [[P]], i32 2
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; CHECK-NEXT: br i1 false, label [[BB2:%.*]], label [[BB1]]
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; CHECK: bb2:
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; CHECK-NEXT: [[I_LCSSA:%.*]] = phi ptr addrspace(7) [ [[I]], [[BB1]] ]
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; CHECK-NEXT: br label [[BB3:%.*]]
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; CHECK: bb3:
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; CHECK-NEXT: [[I4:%.*]] = load i32, ptr addrspace(7) [[I_LCSSA]], align 4
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; CHECK-NEXT: br label [[BB3]]
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;
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bb:
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br label %bb1
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bb1:
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%p = extractelement <2 x ptr addrspace(7)> %arg, i32 0
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%i = getelementptr i32, ptr addrspace(7) %p, i32 2
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br i1 false, label %bb2, label %bb1
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bb2:
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br label %bb3
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bb3:
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%i4 = load i32, ptr addrspace(7) %i, align 4
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br label %bb3
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}
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