f6578c3d80
This patch implements Xtensa ISA option "Windowed Register Option". It implements subtarget feature, instructions descriptions and support of these instructions in asm parser and disassembler. This is the second version of the Windowed Register Option implementation ( previous implementation #121118). In this variant "checkRegister" function is placed in XtensaMCTargetDesc.
69 lines
2.4 KiB
TableGen
69 lines
2.4 KiB
TableGen
//===- Xtensa.td - Describe the Xtensa Target Machine ------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Subtarget Features.
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//===----------------------------------------------------------------------===//
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include "XtensaFeatures.td"
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//===----------------------------------------------------------------------===//
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// Xtensa supported processors.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "XtensaRegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Calling Convention Description
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//===----------------------------------------------------------------------===//
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include "XtensaCallingConv.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "XtensaInstrInfo.td"
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def XtensaInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Target Declaration
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//===----------------------------------------------------------------------===//
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def XtensaAsmParser : AsmParser {
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let ShouldEmitMatchRegisterAltName = 1;
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}
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def XtensaInstPrinter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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}
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def Xtensa : Target {
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let InstructionSet = XtensaInstrInfo;
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let AssemblyWriters = [XtensaInstPrinter];
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let AssemblyParsers = [XtensaAsmParser];
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}
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