89c25c54f9
Implement base windowed register call ABI. By defaullt use rotation window by 8 registers.
129 lines
5.3 KiB
C++
129 lines
5.3 KiB
C++
//===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Xtensa implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
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#define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H
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#include "Xtensa.h"
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#include "XtensaRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "XtensaGenInstrInfo.inc"
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namespace llvm {
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class XtensaTargetMachine;
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class XtensaSubtarget;
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class XtensaInstrInfo : public XtensaGenInstrInfo {
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const XtensaRegisterInfo RI;
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const XtensaSubtarget &STI;
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public:
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XtensaInstrInfo(const XtensaSubtarget &STI);
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void adjustStackPtr(MCRegister SP, int64_t Amount, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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// Return the XtensaRegisterInfo, which this class owns.
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const XtensaRegisterInfo &getRegisterInfo() const { return RI; }
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Register isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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Register isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, Register DestReg, Register SrcReg,
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bool KillSrc, bool RenamableDest = false,
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bool RenamableSrc = false) const override;
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void storeRegToStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool isKill, int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, Register VReg,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
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void loadRegFromStackSlot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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Register DestReg, int FrameIdx, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI, Register VReg,
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MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override;
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// Get the load and store opcodes for a given register class and offset.
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void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode,
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unsigned &StoreOpcode, int64_t offset) const;
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// Emit code before MBBI in MI to move immediate value Value into
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// physical register Reg.
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void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MCRegister *Reg, int64_t Value) const;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB,
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MachineBasicBlock &RestoreBB, const DebugLoc &DL,
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int64_t BrOffset = 0,
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RegScavenger *RS = nullptr) const override;
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unsigned insertBranchAtInst(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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MachineBasicBlock *TBB,
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ArrayRef<MachineOperand> Cond, const DebugLoc &DL,
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int *BytesAdded) const;
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unsigned insertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I,
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int64_t offset,
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ArrayRef<MachineOperand> Cond, DebugLoc DL,
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int *BytesAdded) const;
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// Return true if MI is a conditional or unconditional branch.
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// When returning true, set Cond to the mask of condition-code
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// values on which the instruction will branch, and set Target
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// to the operand that contains the branch target. This target
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// can be a register or a basic block.
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bool isBranch(const MachineBasicBlock::iterator &MI,
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SmallVectorImpl<MachineOperand> &Cond,
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const MachineOperand *&Target) const;
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const XtensaSubtarget &getSubtarget() const { return STI; }
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};
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} // end namespace llvm
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#endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */
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