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clang-p2996/llvm/test/MC/X86
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Fangrui Song 6c2aa37fb1 MCAsmStreamer: Print symbol equated to a register 
GNU Assembler supports `a = %eax` for x86. We use X86MCExpr to support a
register expression. https://reviews.llvm.org/D47545 added reassignment
support but this code is not necessary.
2025-06-28 18:07:43 -07:00
..
AlignedBundling
…
AMX
[X86][APX] Support APX + AMX-MOVRS/AMX-TRANSPOSE (#123267)
2025-01-17 17:51:42 +08:00
apx
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Inputs
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KEYLOCKER
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3DNow.s
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2011-09-06-NoNewline.s
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abs8.s
[X86] Move ABS8 special case to fixupNeedsRelaxationAdvanced
2025-03-18 22:12:33 -07:00
addr16-32.s
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address-size.s
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AES-32.s
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AES-64.s
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align-branch-32bit.s
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align-branch-align.s
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align-branch-basic.s
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align-branch-boundary-default.s
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align-branch-bundle.s
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align-branch-enhanced-relaxation.s
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align-branch-fused.s
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align-branch-general.s
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align-branch-hardcode.s
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align-branch-mixed.s
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align-branch-necessary.s
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align-branch-negative.s
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align-branch-pad-max-prefix.s
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align-branch-prefix.s
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align-branch-relax-all.s
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align-branch-section-size.s
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align-branch-section-type.s
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align-branch-single.s
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align-branch-system.s
…
align-branch-variant-symbol.s
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align-via-padding-corner.s
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align-via-padding.s
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align-via-relaxation.s
…
amx-avx512-att.s
[X86][AMX-AVX512][NFC] Remove P from intrinsic and instruction name (#123270)
2025-01-17 22:21:19 +08:00
amx-avx512-intel.s
[X86][AMX-AVX512][NFC] Remove P from intrinsic and instruction name (#123270)
2025-01-17 22:21:19 +08:00
amx-transpose-att.s
[X86][APX] Support APX + AMX-MOVRS/AMX-TRANSPOSE (#123267)
2025-01-17 17:51:42 +08:00
amx-transpose-intel.s
[X86][APX] Support APX + AMX-MOVRS/AMX-TRANSPOSE (#123267)
2025-01-17 17:51:42 +08:00
avx10_2ni-32-intel.s
Revert "[X86][AVX10.2] Support YMM rounding new instructions (#101825)" (#132362)
2025-03-21 20:12:57 +08:00
avx10_2ni-64-att.s
Revert "[X86][AVX10.2] Support YMM rounding new instructions (#101825)" (#132362)
2025-03-21 20:12:57 +08:00
avx10_2satcvtds-32-att.s
[X86][AVX10.2] Remove YMM rounding from VCVTTP.*QS (#132414)
2025-03-22 01:10:39 +08:00
avx10_2satcvtds-32-intel.s
[X86][AVX10.2] Remove YMM rounding from VCVTTP.*QS (#132414)
2025-03-22 01:10:39 +08:00
avx10_2satcvtds-64-att.s
[X86][AVX10.2] Remove YMM rounding from VCVTTP.*QS (#132414)
2025-03-22 01:10:39 +08:00
avx10_2satcvtds-64-intel.s
[X86][AVX10.2] Remove YMM rounding from VCVTTP.*QS (#132414)
2025-03-22 01:10:39 +08:00
avx10.2-bf16-32-att.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-bf16-32-intel.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-bf16-64-att.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-bf16-64-intel.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-com-ef-32-att.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-com-ef-32-intel.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-com-ef-64-att.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-com-ef-64-intel.s
[X86][AVX10.2] Include changes for COMX and VGETEXP from rev. 2 (#132824)
2025-03-25 13:26:13 +01:00
avx10.2-copy-32-att.s
…
avx10.2-copy-32-intel.s
…
avx10.2-copy-64-att.s
…
avx10.2-copy-64-intel.s
…
avx10.2convert-32-att.s
[X86][AVX10.2] Remove YMM rounding from VCVT2PS2PHX (#132397)
2025-03-21 22:51:51 +08:00
avx10.2convert-32-intel.s
[X86][AVX10.2] Remove YMM rounding from VCVT2PS2PHX (#132397)
2025-03-21 22:51:51 +08:00
avx10.2convert-64-att.s
[X86][AVX10.2] Remove YMM rounding from VCVT2PS2PHX (#132397)
2025-03-21 22:51:51 +08:00
avx10.2convert-64-intel.s
[X86][AVX10.2] Remove YMM rounding from VCVT2PS2PHX (#132397)
2025-03-21 22:51:51 +08:00
avx10.2minmax-32-att.s
[X86][AVX10.2] Remove YMM rounding from VMINMAXP[H,S,D] (#132405)
2025-03-22 00:56:23 +08:00
avx10.2minmax-32-intel.s
[X86][AVX10.2] Remove YMM rounding from VMINMAXP[H,S,D] (#132405)
2025-03-22 00:56:23 +08:00
avx10.2minmax-64-att.s
[X86][AVX10.2] Remove YMM rounding from VMINMAXP[H,S,D] (#132405)
2025-03-22 00:56:23 +08:00
avx10.2minmax-64-intel.s
[X86][AVX10.2] Remove YMM rounding from VMINMAXP[H,S,D] (#132405)
2025-03-22 00:56:23 +08:00
avx10.2satcvt-32-att.s
[X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS (#132426)
2025-03-22 08:42:22 +08:00
avx10.2satcvt-32-intel.s
[X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS (#132426)
2025-03-22 08:42:22 +08:00
avx10.2satcvt-64-att.s
[X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS (#132426)
2025-03-22 08:42:22 +08:00
avx10.2satcvt-64-intel.s
[X86][AVX10.2] Remove YMM rounding from VCVT[,T]PS2I[,U]BS (#132426)
2025-03-22 08:42:22 +08:00
avx512_bf16_vl-32-att.s
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avx512_bf16_vl-32-intel.s
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avx512_bf16_vl-64-att.s
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avx512_bf16_vl-64-intel.s
…
avx512_bf16-32-att.s
…
avx512_bf16-32-intel.s
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avx512_bf16-64-att.s
…
avx512_bf16-64-intel.s
…
avx512-att-errors.s
…
avx512-att.s
…
avx512-intel-errors.s
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avx512-intel.s
[X86] Use loaded/stored element size when parsing/printing gather/scatter pointer size in Intel syntax. (#122530)
2025-01-13 10:36:40 -08:00
avx512bitalg-att.s
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avx512bitalg-intel.s
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avx512bw_vl-64-att.s
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avx512bw-64-att.s
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avx512bw-att.s
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avx512cd_vl-att.s
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avx512cd-att.s
…
avx512dq_vl-att.s
…
avx512dq_vl-intel.s
…
avx512dq-att.s
…
avx512f_vl-att.s
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avx512f_vl-intel.s
[X86] Use loaded/stored element size when parsing/printing gather/scatter pointer size in Intel syntax. (#122530)
2025-01-13 10:36:40 -08:00
avx512fp16-att.s
…
avx512fp16-complex-fma_vl.s
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avx512fp16-complex-fma.s
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avx512fp16-intel.s
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avx512fp16vl-att.s
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avx512fp16vl-intel.s
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avx512gfni-att.s
[X86] Correct the cdisp8 encoding for VGF2P8AFFINEINVQB and VGF2P8AFFINEQB. (#120340)
2024-12-17 21:36:36 -08:00
avx512ifma-att.s
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avx512ifmavl-att.s
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avx512pf-64-att.s
[X86] Correct the cdisp8 encoding for VSCATTER/VGATHER prefetch (#122051)
2025-01-11 16:51:20 +08:00
avx512vaes-att.s
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avx512vbmi2-att.s
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avx512vbmi2vl-att.s
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avx512vbmi_vl-intel.s
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avx512vbmi-att.s
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avx512vbmi-intel.s
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avx512vl_bitalg-att.s
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avx512vl_gfni-att.s
[X86] Correct the cdisp8 encoding for VGF2P8AFFINEINVQB and VGF2P8AFFINEQB. (#120340)
2024-12-17 21:36:36 -08:00
avx512vl_vaes-att.s
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avx512vl_vnni-att.s
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avx512vl-att.s
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avx512vlvpclmul.s
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avx512vnni-att.s
…
avx512vp2intersect-32-att.s
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avx512vp2intersect-32-intel.s
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avx512vp2intersect-64-att.s
…
avx512vp2intersect-64-intel.s
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avx512vp2intersectvl-32-att.s
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avx512vp2intersectvl-32-intel.s
…
avx512vp2intersectvl-64-att.s
…
avx512vp2intersectvl-64-intel.s
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avx512vpclmul.s
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avx512vpopcntdq-64-att.s
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avx5124fmaps-att.s
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avx5124vnniw-att.s
…
AVX2-32.s
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AVX2-64.s
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AVX512F_512-32.s
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AVX512F_512-64.s
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AVX512F_SCALAR-32.s
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AVX512F_SCALAR-64.s
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avx_clmul-att.s
…
avx_ne_convert-32-att.s
…
avx_ne_convert-32-intel.s
…
avx_ne_convert-64-att.s
…
avx_ne_convert-64-intel.s
…
avx_vaes-att.s
…
avx_vnni_int8-32-att.s
…
avx_vnni_int8-32-intel.s
…
avx_vnni_int8-64-att.s
…
avx_vnni_int8-64-intel.s
…
avx_vnni-32-intel.s
…
avx_vnni-64-att.s
…
avx_vnni-64-intel.s
…
avx_vnni-att-32.s
…
avx-32-att.s
…
avx-64-att.s
…
avx-64-intel.s
[X86] Use loaded/stored element size when parsing/printing gather/scatter pointer size in Intel syntax. (#122530)
2025-01-13 10:36:40 -08:00
AVX-32.s
…
AVX-64.s
…
avx-ifma-att-32.s
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avx-ifma-att-64.s
…
avx-ifma-intel-32.s
…
avx-ifma-intel-64.s
…
avx-vnni-int16-32-att.s
…
avx-vnni-int16-32-intel.s
…
avx-vnni-int16-64-att.s
…
avx-vnni-int16-64-intel.s
…
AVXAES-32.s
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AVXAES-64.s
…
BMI1-32.s
…
BMI1-64.s
…
BMI2-32.s
…
BMI2-64.s
…
bmi-att.s
…
CET-32.s
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CET-64.s
…
cet-att.s
…
cfi_offset-eip.s
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check-end-of-data-region.s
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CLFLUSHOPT-32.s
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CLFLUSHOPT-64.s
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CLFSH-32.s
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CLFSH-64.s
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CLWB-32.s
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CLWB-64.s
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CLZERO-32.s
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CLZERO-64.s
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cmpccxadd-att-alias.s
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cmpccxadd-att.s
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cmpccxadd-intel-alias.s
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cmpccxadd-intel.s
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code16-32-64.s
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code16gcc-align.s
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code16gcc.s
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compact-unwind-cfi_def_cfa.s
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compact-unwind-mode-dwarf.s
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compact-unwind.s
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crlf.test
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data-prefix16.s
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data-prefix32.s
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data-prefix64.s
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data-prefix-fail.s
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directive-arch.s
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directive-quad.s
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disassemble-zeroes.s
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displacement-overflow.s
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dwarf-segment-register.s
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dwarf-size-field-overflow.test
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elf-reloc-got.s
[X86] Improve GOT/PLTOFF on local symbol tests
2025-05-22 09:27:53 -07:00
elf-reloc-size.s
[test] Reorganize some R_X86_64_ tests
2024-12-14 22:11:58 -08:00
elf-reloc-tls.s
[test] Reorganize some R_X86_64_ tests
2024-12-14 22:11:58 -08:00
encoder-fail.s
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error-reloc.s
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eval-fill.s
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F16C-32.s
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F16C-64.s
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faultmap-section-parsing.s
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fixup-cpu-mode.s
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fma3-att.s
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fma4-att.s
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FMA-32.s
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FMA-64.s
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fp-setup-macho.s
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fred-att.s
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fred-intel.s
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FXSAVE64-64.s
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FXSAVE-32.s
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FXSAVE-64.s
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gather.s
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gfni-att.s
…
gnux32-dwarf-gen.s
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gotpcrel_norelax.s
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gotpcrel-non-globals.ll
[AsmPrinter] Always emit global equivalents if there is non-global uses (#145648)
2025-06-25 18:39:36 +08:00
gotpcrelx.s
[X86] Improve GOT/PLTOFF on local symbol tests
2025-05-22 09:27:53 -07:00
hex-immediates.s
…
hle-att.s
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i386-darwin-frame-register.ll
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I86-32.s
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I86-64.s
…
I186-32.s
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I186-64.s
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I286-32.s
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I286-64.s
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I386-32.s
[X86][AsmParser] Improve rel8 validation (#126073)
2025-03-06 21:45:16 +01:00
I386-64.s
[X86][AsmParser] Improve rel8 validation (#126073)
2025-03-06 21:45:16 +01:00
I486-32.s
…
I486-64.s
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imm-comments.s
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index-operations.s
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inline-asm-obj.ll
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intel-syntax-2.s
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intel-syntax-32.s
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intel-syntax-ambiguous.s
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intel-syntax-bitwise-ops.s
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intel-syntax-branch.s
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intel-syntax-directional-label.s
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intel-syntax-encoding.s
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intel-syntax-error.s
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intel-syntax-expr.s
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intel-syntax-hex.s
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intel-syntax-invalid-basereg.s
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intel-syntax-invalid-scale.s
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intel-syntax-print.ll
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intel-syntax-ptr-sized.s
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intel-syntax-unsized-memory.s
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intel-syntax-var-offset.ll
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intel-syntax.s
[X86][AsmParser] Improve rel8 validation (#126073)
2025-03-06 21:45:16 +01:00
invalid_opcode.s
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INVPCID-32.s
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INVPCID-64.s
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large-bss.s
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line-table-sections.s
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lit.local.cfg
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lkgs-att.s
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lkgs-intel.s
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lwp-64-att.s
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LWP-32.s
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LWP-64.s
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lwp-att.s
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macho-reloc-errors-x86_64.s
[MC] Rework evaluateSymbolicAdd to eliminate MCValue::SymB reliance
2025-04-05 11:16:12 -07:00
macho-reloc-errors-x86.s
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maskmovdqu64.s
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maskmovdqu.s
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MMX-32.s
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MMX-64.s
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movrs-att-64.s
[X86][APX] Support APX + MOVRS (#123264)
2025-01-17 16:06:31 +08:00
movrs-avx10-att-64.s
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movrs-avx10-intel-64.s
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movrs-intel-64.s
[X86][APX] Support APX + MOVRS (#123264)
2025-01-17 16:06:31 +08:00
msrimm-64-att.s
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msrimm-64-intel.s
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msrlist-64-att.s
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no-elf-compact-unwind.s
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pad-for-align-debug.s
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padlock.s
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pbndkb.s
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PKU-32.s
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PKU-64.s
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pltoff.s
[X86] Improve GOT/PLTOFF on local symbol tests
2025-05-22 09:27:53 -07:00
POPCNT-32.s
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POPCNT-64.s
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PPRO-32.s
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PPRO-64.s
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pr22004.s
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pr22028.s
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pr27884.s
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pr28547.s
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pr32530.s
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PREFETCH-32.s
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PREFETCH-64.s
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prefetchit-non-rip-op.s
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prefetchrst2-att-32.s
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prefetchrst2-att-64.s
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prefetchrst2-intel-32.s
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prefetchrst2-intel-64.s
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prefix-padding-32.s
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prefix-padding-64.s
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pseudo-rex.s
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rand-att.s
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rao-int-att.s
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rao-int-intel.s
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raoint-64-att.s
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raoint-64-intel.s
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RDPMC-32.s
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RDPMC-64.s
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RDPRU.s
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RDRAND-32.s
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RDRAND-64.s
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RDSEED-32.s
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RDSEED-64.s
…
RDTSCP-32.s
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RDTSCP-64.s
…
RDWRFSGS-64.s
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register-assignment.s
MCAsmStreamer: Print symbol equated to a register
2025-06-28 18:07:43 -07:00
relax-insn.s
…
relax-offset.s
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reloc-directive-elf-32.s
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reloc-directive-elf-64.s
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reloc-directive.s
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reloc-macho.s
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reloc-undef-global.s
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ret.s
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rtm-att.s
…
RTM.s
…
segment-prefix.s
…
sha512-32-att.s
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sha512-32-intel.s
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sha512-64-att.s
…
sha512-64-intel.s
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SHA-32.s
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SHA-64.s
…
shuffle-comments.s
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signed-coff-pcrel.s
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sm3-att-32.s
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sm3-att-64.s
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sm3-intel-32.s
…
sm3-intel-64.s
…
sm4-32-att.s
…
sm4-32-intel.s
…
sm4-64-att.s
…
sm4-64-intel.s
…
sm4-evex-32-att.s
…
sm4-evex-32-intel.s
…
sm4-evex-64-att.s
…
sm4-evex-64-intel.s
…
SNP-32.s
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SNP-64.s
…
space-err.s
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sse4a-att.s
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SSE2-32.s
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SSE2-64.s
…
SSE3-32.s
…
SSE3-64.s
…
SSE4a-32.s
…
SSE4a-64.s
…
SSE41-32.s
…
SSE41-64.s
…
SSE42-32.s
…
SSE42-64.s
…
SSE_PREFETCH-32.s
…
SSE_PREFETCH-64.s
…
SSE-32.s
…
SSE-64.s
…
SSEMXCSR-32.s
…
SSEMXCSR-64.s
…
SSSE3-32.s
…
SSSE3-64.s
…
stackmap-nops.ll
…
stdcall.s
…
SVM-32.s
…
SVM-64.s
…
tbm-att.s
…
tlsdesc-32.s
…
tlsdesc-64.s
[X86][MC] Support R_X86_64_CODE_4_GOTPC32_TLSDESC (#116908)
2024-11-22 09:25:19 +08:00
tlsdesc-x32.s
…
usermsr-64-att.s
…
usermsr-64-intel.s
…
validate-inst-att.s
…
validate-inst-intel.s
[X86][AsmParser] Improve rel8 validation (#126073)
2025-03-06 21:45:16 +01:00
variant-diagnostics.s
…
vinsertps_decode.s
…
VMFUNC-32.s
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VMFUNC-64.s
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vpclmulqdq.s
…
VTX-32.s
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VTX-64.s
…
win-import-call-optimization.s
[x64][win] Add compiler support for x64 import call optimization (equivalent to MSVC /d2guardretpoline) (#126631)
2025-05-20 14:48:41 -07:00
wrmsrns.s
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x86_64-asm-match.s
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x86_64-directive-nops.s
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x86_64-encoding.s
…
x86_64-imm-widths.s
…
x86_64-signed-reloc.s
…
x86_directives.s
…
x86_errors.s
…
x86_long_nop.s
…
x86_nop.s
…
x86_operands.s
…
x86-16.s
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x86-32-coverage.s
…
x86-32-fma3.s
…
x86-32-ms-inline-asm.s
…
x86-32.s
…
x86-64.s
…
x86-branch-relaxation.s
…
x86-directive-nops-errors.s
…
x86-directive-nops.s
…
x86-evenDirective.s
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x86-GCC-inline-asm-Y-constraints.ll
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x86-itanium.ll
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x86-jcxz-loop-fixup.s
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x86-target-directives.s
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x86-windows-itanium-libcalls.ll
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X86_64-pku.s
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X87-32.s
…
X87-64.s
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XOP-32.s
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XOP-64.s
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xop-att.s
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XSAVE-32.s
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XSAVE-64.s
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XSAVEC-32.s
…
XSAVEC-64.s
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XSAVEOPT-32.s
…
XSAVEOPT-64.s
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XSAVES-32.s
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XSAVES-64.s
…