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clang-p2996/llvm/lib/Target/RISCV
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Fraser Cormack a4729f7f88 [RISCV] Lower RVV vector SELECTs to VSELECTs 
This patch optimizes the code generation of vector-type SELECTs (LLVM
select instructions with scalar conditions) by custom-lowering to
VSELECTs (LLVM select instructions with vector conditions) by splatting
the condition to a vector. This avoids the default expansion path which
would either introduce control flow or fully scalarize.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104772
2021-06-24 10:12:51 +01:00
..
AsmParser
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
Disassembler
…
MCTargetDesc
RISCV: clean up target expression handling
2021-06-17 13:35:32 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.h
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.td
[RISCV][NFC] Fix formatting
2021-04-09 14:41:09 +08:00
RISCVAsmPrinter.cpp
[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.
2021-05-10 09:33:23 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVFrameLowering.cpp
[RISCV] Avoid scalar outgoing argumetns overwriting vector frame objects.
2021-06-11 12:26:29 +08:00
RISCVFrameLowering.h
[RISCV] Fix offset computation for RVV
2021-03-29 17:03:49 +00:00
RISCVInsertVSETVLI.cpp
[RISCV] Remove extra character from a comment. NFC
2021-06-21 12:52:02 -07:00
RISCVInstrFormats.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.
2021-06-21 11:27:44 -07:00
RISCVInstrInfo.h
Further improve register allocation for vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.
2021-06-08 09:43:43 -07:00
RISCVInstrInfo.td
[RISCV] Optimize add-mul in the zba extension with SH*ADD
2021-06-19 14:33:27 +08:00
RISCVInstrInfoA.td
[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
2021-04-09 09:37:04 +08:00
RISCVInstrInfoB.td
[RISCV] Prevent formation of shXadd(.uw) and add.uw if it prevents the use of addi.
2021-06-19 12:10:42 -07:00
RISCVInstrInfoC.td
[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.
2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrInfoF.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrInfoM.td
[RISCV] Add custom type legalization to form MULHSU when possible.
2021-04-01 10:15:55 -07:00
RISCVInstrInfoV.td
[RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.
2021-04-21 14:50:29 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.
2021-06-21 11:27:44 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.
2021-06-21 11:27:44 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add isel patterns to match vmacc/vmadd/vnmsub/vnmsac from add/sub and mul.
2021-06-21 11:27:44 -07:00
RISCVInstrInfoZfh.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Add explicit copy to V0 in the masked vmsge(u).vx intrinsic handling.
2021-06-23 08:04:42 -07:00
RISCVISelDAGToDAG.h
[RISCV] Use bitfields to shrink the size of the vector load/store intrinsics to pseudo instruction lookup tables.
2021-06-07 17:57:51 -07:00
RISCVISelLowering.cpp
[RISCV] Lower RVV vector SELECTs to VSELECTs
2021-06-24 10:12:51 +01:00
RISCVISelLowering.h
[RISCV] Transform unaligned RVV vector loads/stores to aligned ones
2021-06-14 18:12:18 +01:00
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
[RISCV] Don't emit save-restore call if function is a interrupt handler
2021-04-16 12:54:47 +08:00
RISCVMCInstLower.cpp
[RISCV] Move instruction information into the RISCVII namespace (NFC)
2021-05-11 16:32:42 -05:00
RISCVMergeBaseOffset.cpp
…
RISCVRegisterBankInfo.cpp
…
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Reserve an emergency spill slot for any RVV spills
2021-06-03 10:44:34 +01:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Introduce floating point control and state registers
2021-04-21 12:55:30 +07:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVSchedSiFive7.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVSchedule.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVScheduleB.td
[RISCV] Move scheduling resources for B into a separate file (NFC)
2021-03-29 20:37:22 -05:00
RISCVSubtarget.cpp
[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
2021-04-23 15:06:20 -07:00
RISCVSubtarget.h
[RISCV] Don't enable loop vectorizer interleaving if the V extension isn't enabled.
2021-06-07 10:20:59 -07:00
RISCVSystemOperands.td
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add support for fmin/fmax vector reductions
2021-05-03 10:33:51 +01:00
RISCVTargetTransformInfo.h
[RISCV] Don't enable Interleaved Access Vectorization
2021-06-18 12:32:30 +08:00