fad70c3068
Recently we improved the lowering of low overhead loops and tail
predicated loops, but concentrated first on the DLS do style loops. This
extends those improvements over to the WLS while loops, improving the
chance of lowering them successfully. To do this the lowering has to
change a little as the instructions are terminators that produce a value
- something that needs to be treated carefully.
Lowering starts at the Hardware Loop pass, inserting a new
llvm.test.start.loop.iterations that produces both an i1 to control the
loop entry and an i32 similar to the llvm.start.loop.iterations
intrinsic added for do loops. This feeds into the loop phi, properly
gluing the values together:
%wls = call { i32, i1 } @llvm.test.start.loop.iterations.i32(i32 %div)
%wls0 = extractvalue { i32, i1 } %wls, 0
%wls1 = extractvalue { i32, i1 } %wls, 1
br i1 %wls1, label %loop.ph, label %loop.exit
...
loop:
%lsr.iv = phi i32 [ %wls0, %loop.ph ], [ %iv.next, %loop ]
..
%iv.next = call i32 @llvm.loop.decrement.reg.i32(i32 %lsr.iv, i32 1)
%cmp = icmp ne i32 %iv.next, 0
br i1 %cmp, label %loop, label %loop.exit
The llvm.test.start.loop.iterations need to be lowered through ISel
lowering as a pair of WLS and WLSSETUP nodes, which each get converted
to t2WhileLoopSetup and t2WhileLoopStart Pseudos. This helps prevent
t2WhileLoopStart from being a terminator that produces a value,
something difficult to control at that stage in the pipeline. Instead
the t2WhileLoopSetup produces the value of LR (essentially acting as a
lr = subs rn, 0), t2WhileLoopStart consumes that lr value (the Bcc).
These are then converted into a single t2WhileLoopStartLR at the same
point as t2DoLoopStartTP and t2LoopEndDec. Otherwise we revert the loop
to prevent them from progressing further in the pipeline. The
t2WhileLoopStartLR is a single instruction that takes a GPR and produces
LR, similar to the WLS instruction.
%1:gprlr = t2WhileLoopStartLR %0:rgpr, %bb.3
t2B %bb.1
...
bb.2.loop:
%2:gprlr = PHI %1:gprlr, %bb.1, %3:gprlr, %bb.2
...
%3:gprlr = t2LoopEndDec %2:gprlr, %bb.2
t2B %bb.3
The t2WhileLoopStartLR can then be treated similar to the other low
overhead loop pseudos, eventually being lowered to a WLS providing the
branches are within range.
Differential Revision: https://reviews.llvm.org/D97729
196 lines
8.8 KiB
YAML
196 lines
8.8 KiB
YAML
# RUN: llc -O0 -run-pass=arm-low-overhead-loops -o - -verify-machineinstrs %s | FileCheck %s
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# CHECK-NOT: WLS
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# CHECK-NOT: WhileLoopStart
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main"
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define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) #0 {
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entry:
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br label %while
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for.cond.cleanup: ; preds = %while, %for.body
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ret void
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for.body.preheader: ; preds = %while
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%scevgep = getelementptr i32, i32* %a, i32 -1
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%scevgep4 = getelementptr i32, i32* %c, i32 -1
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%scevgep8 = getelementptr i32, i32* %b, i32 -1
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br label %for.body
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for.body: ; preds = %for.body, %for.body.preheader
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%lsr.iv9 = phi i32* [ %scevgep8, %for.body.preheader ], [ %scevgep10, %for.body ]
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%lsr.iv5 = phi i32* [ %scevgep4, %for.body.preheader ], [ %scevgep6, %for.body ]
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%lsr.iv1 = phi i32* [ %scevgep, %for.body.preheader ], [ %scevgep2, %for.body ]
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%0 = phi i32 [ %N, %for.body.preheader ], [ %3, %for.body ]
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%scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1
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%1 = load i32, i32* %scevgep11, align 4
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%scevgep7 = getelementptr i32, i32* %lsr.iv5, i32 1
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%2 = load i32, i32* %scevgep7, align 4
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%mul = mul nsw i32 %2, %1
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%scevgep3 = getelementptr i32, i32* %lsr.iv1, i32 1
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store i32 %mul, i32* %scevgep3, align 4
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%scevgep2 = getelementptr i32, i32* %lsr.iv1, i32 1
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%scevgep6 = getelementptr i32, i32* %lsr.iv5, i32 1
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%scevgep10 = getelementptr i32, i32* %lsr.iv9, i32 1
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%3 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
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%4 = icmp ne i32 %3, 0
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br i1 %4, label %for.body, label %for.cond.cleanup
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while: ; preds = %entry
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%cmp8 = call i1 @llvm.test.set.loop.iterations.i32(i32 %N)
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br i1 %cmp8, label %for.body.preheader, label %for.cond.cleanup
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}
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; Function Attrs: nounwind
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declare i32 @llvm.arm.space(i32 immarg, i32) #1
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; Function Attrs: noduplicate nounwind
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declare i1 @llvm.test.set.loop.iterations.i32(i32) #2
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; Function Attrs: noduplicate nounwind
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #2
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attributes #0 = { "target-features"="+lob" }
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attributes #1 = { nounwind }
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attributes #2 = { noduplicate nounwind }
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...
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---
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name: size_limit
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 40
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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successors: %bb.4(0x80000000)
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liveins: $r0, $r1, $r2, $r3, $r4, $lr
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frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r4, -8
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$sp = frame-setup tSUBspi $sp, 8, 14, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_offset 40
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tSTRspi killed $r3, $sp, 7, 14, $noreg :: (store 4 into %stack.0)
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tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1)
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tSTRspi killed $r1, $sp, 5, 14, $noreg :: (store 4 into %stack.2)
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tSTRspi killed $r0, $sp, 4, 14, $noreg :: (store 4 into %stack.3)
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tB %bb.4, 14, $noreg
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bb.1.for.cond.cleanup:
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$sp = tADDspi $sp, 8, 14, $noreg
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tPOP_RET 14, $noreg, def $r4, def $pc
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bb.2.for.body.preheader:
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successors: %bb.3(0x80000000)
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$r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3)
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renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg
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$r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1)
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renamable $r3, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
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$r12 = t2LDRi12 $sp, 20, 14, $noreg :: (load 4 from %stack.2)
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renamable $lr = t2SUBri killed renamable $r12, 4, 14, $noreg, $noreg
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$r4 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0)
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t2STRi12 killed $lr, $sp, 12, 14, $noreg :: (store 4 into %stack.4)
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tSTRspi killed $r3, $sp, 2, 14, $noreg :: (store 4 into %stack.5)
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tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6)
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tSTRspi killed $r4, $sp, 0, 14, $noreg :: (store 4 into %stack.7)
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tB %bb.3, 14, $noreg
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bb.3.for.body:
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successors: %bb.3(0x40000000), %bb.1(0x40000000)
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$r0 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7)
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$r1 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6)
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$r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5)
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$r3 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4)
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renamable $r12, renamable $r3 = t2LDR_PRE renamable $r3, 4, 14, $noreg :: (load 4 from %ir.scevgep11)
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renamable $lr, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
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renamable $r12 = nsw t2MUL killed renamable $lr, killed renamable $r12, 14, $noreg
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early-clobber renamable $r1 = t2STR_PRE killed renamable $r12, renamable $r1, 4, 14, $noreg :: (store 4 into %ir.scevgep3)
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$lr = tMOVr killed $r0, 14, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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$r0 = tMOVr $lr, 14, $noreg
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tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7)
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tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6)
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tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5)
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tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4)
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t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr
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tB %bb.1, 14, $noreg
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bb.4.while:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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$r0 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0)
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$lr = t2WhileLoopStartLR killed renamable $r0, %bb.1, implicit-def dead $cpsr
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tB %bb.2, 14, $noreg
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...
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