422bf13f33
…return only Load since other output is chain.
Added testcase that showed mismatched expected arity when Load and chain
were returned as separate items after
003b58f65b
196 lines
7.1 KiB
LLVM
196 lines
7.1 KiB
LLVM
; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefixes=R600,ALL
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; RUN: llc < %s -mtriple=amdgcn -verify-machineinstrs | FileCheck %s --check-prefixes=GFX6,GFX678,ALL
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; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefixes=GFX8,GFX678,ALL
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; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX10,GFX1011,ALL
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; RUN: llc < %s -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs | FileCheck %s --check-prefixes=GFX11,GFX1011,ALL
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; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx940 | FileCheck %s --check-prefixes=GFX940,ALL
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; ALL-LABEL: {{^}}build_vector2:
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; R600: MOV
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; R600: MOV
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; R600-NOT: MOV
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; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX678: buffer_store_dwordx2 v[[[X]]:[[Y]]]
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; GFX10: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX11: global_store_b64 v2, v[0:1], s[0:1]
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define amdgpu_kernel void @build_vector2 (ptr addrspace(1) %out) {
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entry:
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store <2 x i32> <i32 5, i32 6>, ptr addrspace(1) %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector4:
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; R600: MOV
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; R600: MOV
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; R600: MOV
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; R600: MOV
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; R600-NOT: MOV
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; GFX678-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX678-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX678-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
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; GFX678-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
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; GFX1011-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5
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; GFX1011-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6
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; GFX1011-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7
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; GFX1011-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8
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; GFX678: buffer_store_dwordx4 v[[[X]]:[[W]]]
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; GFX10: global_store_dwordx4 v4, v[0:3], s[0:1]
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; GFX11: global_store_b128 v4, v[0:3], s[0:1]
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define amdgpu_kernel void @build_vector4 (ptr addrspace(1) %out) {
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entry:
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store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, ptr addrspace(1) %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector_v2i16:
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; R600: MOV
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; R600-NOT: MOV
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; GFX678: s_mov_b32 s3, 0xf000
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; GFX678: s_mov_b32 s2, -1
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; GFX678: v_mov_b32_e32 v0, 0x60005
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; GFX678: s_waitcnt lgkmcnt(0)
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; GFX678: buffer_store_dword v0, off, s[0:3], 0
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; GFX1011: v_mov_b32_e32 v0, 0
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; GFX1011: v_mov_b32_e32 v1, 0x60005
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; GFX1011: s_waitcnt lgkmcnt(0)
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; GFX10: global_store_dword v0, v1, s[0:1]
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; GFX11: global_store_b32 v0, v1, s[0:1]
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define amdgpu_kernel void @build_vector_v2i16 (ptr addrspace(1) %out) {
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entry:
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store <2 x i16> <i16 5, i16 6>, ptr addrspace(1) %out
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ret void
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}
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; ALL-LABEL: {{^}}build_vector_v2i16_trunc:
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; R600: LSHR
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; R600: OR_INT
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; R600: LSHR
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; R600-NOT: MOV
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; GFX6: s_mov_b32 s3, 0xf000
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; GFX6: s_waitcnt lgkmcnt(0)
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; GFX6: v_alignbit_b32 v0, 5, s4, 16
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; GFX6: buffer_store_dword v0, off, s[0:3], 0
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; GFX8: s_mov_b32 s3, 0xf000
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; GFX8: s_mov_b32 s2, -1
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; GFX8: s_waitcnt lgkmcnt(0)
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; GFX8: s_lshr_b32 s4, s4, 16
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; GFX8: s_or_b32 s4, s4, 0x50000
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; GFX8: v_mov_b32_e32 v0, s4
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; GFX8: buffer_store_dword v0, off, s[0:3], 0
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; GFX1011: v_mov_b32_e32 v0, 0
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; GFX1011: s_waitcnt lgkmcnt(0)
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; GFX10: s_lshr_b32 s2, s2, 16
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; GFX10: s_pack_ll_b32_b16 s2, s2, 5
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; GFX11: s_pack_hl_b32_b16 s2, s2, 5
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; GFX1011: v_mov_b32_e32 v1, s2
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; GFX10: global_store_dword v0, v1, s[0:1]
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; GFX11: global_store_b32 v0, v1, s[0:1]
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define amdgpu_kernel void @build_vector_v2i16_trunc (ptr addrspace(1) %out, i32 %a) {
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%srl = lshr i32 %a, 16
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%trunc = trunc i32 %srl to i16
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%ins.0 = insertelement <2 x i16> undef, i16 %trunc, i32 0
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%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
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store <2 x i16> %ins.1, ptr addrspace(1) %out
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ret void
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}
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; R600-LABEL: build_v2i32_from_v4i16_shuffle:
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; R600: ; %bb.0: ; %entry
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; R600-NEXT: ALU 0, @10, KC0[], KC1[]
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; R600-NEXT: TEX 1 @6
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; R600-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]
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; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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; R600-NEXT: CF_END
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; R600-NEXT: PAD
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; R600-NEXT: Fetch clause starting at 6:
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; R600-NEXT: VTX_READ_16 T1.X, T0.X, 48, #3
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; R600-NEXT: VTX_READ_16 T0.X, T0.X, 44, #3
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; R600-NEXT: ALU clause starting at 10:
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; R600-NEXT: MOV * T0.X, 0.0,
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; R600-NEXT: ALU clause starting at 11:
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; R600-NEXT: LSHL * T0.Y, T1.X, literal.x,
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; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
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; R600-NEXT: LSHL T0.X, T0.X, literal.x,
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; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
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; R600-NEXT: 16(2.242078e-44), 2(2.802597e-45)
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;
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; GFX6-LABEL: build_v2i32_from_v4i16_shuffle:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_lshl_b32 s3, s3, 16
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; GFX6-NEXT: s_lshl_b32 s2, s2, 16
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s4, s0
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; GFX6-NEXT: s_mov_b32 s5, s1
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; GFX6-NEXT: v_mov_b32_e32 v0, s2
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; GFX6-NEXT: v_mov_b32_e32 v1, s3
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; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX8-LABEL: build_v2i32_from_v4i16_shuffle:
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; GFX8: ; %bb.0: ; %entry
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX8-NEXT: s_mov_b32 s7, 0xf000
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; GFX8-NEXT: s_mov_b32 s6, -1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: s_mov_b32 s4, s0
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; GFX8-NEXT: s_mov_b32 s5, s1
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; GFX8-NEXT: s_lshl_b32 s0, s3, 16
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; GFX8-NEXT: s_lshl_b32 s1, s2, 16
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; GFX8-NEXT: v_mov_b32_e32 v0, s1
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; GFX8-NEXT: v_mov_b32_e32 v1, s0
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; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GFX8-NEXT: s_endpgm
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;
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; GFX10-LABEL: build_v2i32_from_v4i16_shuffle:
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; GFX10: ; %bb.0: ; %entry
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0
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; GFX10-NEXT: v_mov_b32_e32 v2, 0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_lshl_b32 s2, s2, 16
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; GFX10-NEXT: s_lshl_b32 s3, s3, 16
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; GFX10-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-NEXT: v_mov_b32_e32 v1, s3
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; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: build_v2i32_from_v4i16_shuffle:
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; GFX11: ; %bb.0: ; %entry
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; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0
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; GFX11-NEXT: v_mov_b32_e32 v2, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_lshl_b32 s2, s2, 16
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; GFX11-NEXT: s_lshl_b32 s3, s3, 16
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; GFX11-NEXT: v_mov_b32_e32 v0, s2
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; GFX11-NEXT: v_mov_b32_e32 v1, s3
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; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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;
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; GFX940-LABEL: build_v2i32_from_v4i16_shuffle:
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; GFX940: ; %bb.0: ; %entry
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; GFX940-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX940-NEXT: v_mov_b32_e32 v2, 0
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; GFX940-NEXT: s_waitcnt lgkmcnt(0)
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; GFX940-NEXT: s_lshl_b32 s3, s3, 16
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; GFX940-NEXT: s_lshl_b32 s2, s2, 16
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; GFX940-NEXT: v_mov_b32_e32 v0, s2
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; GFX940-NEXT: v_mov_b32_e32 v1, s3
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; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] sc0 sc1
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; GFX940-NEXT: s_endpgm
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define amdgpu_kernel void @build_v2i32_from_v4i16_shuffle(ptr addrspace(1) %out, <4 x i16> %in) {
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entry:
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%shuf = shufflevector <4 x i16> %in, <4 x i16> zeroinitializer, <2 x i32> <i32 0, i32 2>
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%zextended = zext <2 x i16> %shuf to <2 x i32>
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%shifted = shl <2 x i32> %zextended, <i32 16, i32 16>
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store <2 x i32> %shifted, ptr addrspace(1) %out
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ret void
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}
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